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| Patterson D.A., Hennessy J.L. — Computer Organization and Design: The Hardware/Software Interface |
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| Ïðåäìåòíûé óêàçàòåëü |
Pipdining hazards data, stalls 413—416
Pipdining hazards data, structural 375
Pipeline stalls 377—379 413—416 CD6.7:5—7
Pipelining hazards, branch/control 379—382 416—424 CD6.7:8—9
Pipelining, advanced methods for extracting more performance 432—445
Pipelining, control 399—402
Pipelining, datapath 384—399
Pipelining, defined 370
Pipelining, designing instruction sets for 374—375
Pipelining, exceptions 427—432
Pipelining, fallacies and pitfalls 451—384
Pipelining, forwarding 376—377 402—412 CD6.7:3
Pipelining, graphic representation 395—399
Pipelining, historical development of CD6.13:1—13
Pipelining, instruction execution sped up by 372—374
Pipelining, latency 383
Pipelining, overview of 370
Pipelining, Pentium 4 example 448
Pipelining, stalls 377—379 413—416 CD6.7:5—7
Pipelining, Verilog used to describe and model CD6.7:l—9
Pitfalls 33—34
pixels 18
Pointers, arrays versus 130—134
Poison 442
polling 590
pop 80
Pop-up satellite archival tags (PSATs) 156—157
Positive numbers, multiplying 176—180
Power 30—32
Power, consumption, problems with 263—265
PowerPC, addressing IMD2:17—20
PowerPC, instructions D32—33
PowerPC, multiply-add instruction IMD3:10
Prediction 382 421—423
Prediction, IA-64 441
preserving registers 127
primary memory 23
Procedure call conventions A22—33
Procedure call frame A23
Procedures, allocating space for data on heap 87—88
Procedures, allocating space for data on stack 86
Procedures, C 81—88
procedures, defined 79
Procedures, frame 86
Procedures, inlining 116
Procedures, leaf 83 93
Procedures, nested 83—85
Procedures, preserved versus not preserved 85
Procedures, recursive A26 29
Procedures, steps 70
Process switch 530
Processor 20
Processor, -memory buses 582
Processor, communicating with 590—591
Processor, cores 6—7
Product of sums B10—12
Product terms B12
Program counter (PC) 80 292
Programmable logic arrays (PLAs) B12—14 C7 19—20
Programmable logic devices (PLDs) B77
Programmable read only memory (PROM) Â14 16
Programming languages, history of CD2.19:6—7
Propagate, carry lookahead B39—47
Propagation time B77
Protection group 576
Protocol families/suites CD8.3:1—2
protocol stack CD8.3:3
Pseudodirect addressing 100
Pseudoinstructions 107 A17
push 80
Putzolu, Gianfranco CD8.11:5
Quicksort 129 507—508
Quotient 183
R-type instructions 292—293 298
Radio communication CD8.3:8—9
Radix sort 507—508
RAID (redundant arrays of inexpensive disks), big-interleaved parity (RAID 3) 576—577
RAID (redundant arrays of inexpensive disks), block-interleaved parity (RAID 4) 577—578
RAID (redundant arrays of inexpensive disks), distributed block-interleaved parity (RAID 5) 578
RAID (redundant arrays of inexpensive disks), error detecting and correcting code (RAID 2) 575
RAID (redundant arrays of inexpensive disks), historical development of CD8.11:5—6
RAID (redundant arrays of inexpensive disks), mirroring (RAID 1) 575
RAID (redundant arrays of inexpensive disks), no redundancy (RAID 0) 575
RAID (redundant arrays of inexpensive disks), P + Q redundancy (RAID 6) 578
RAID (redundant arrays of inexpensive disks), summary of 578—579
RAID (redundant arrays of inexpensive disks), use of term 574—574
Random access memory (RAM) 20
Raster cathode ray tubes (CRTs) 18
Raster refresh buffer 18
Rau, Bob CD6.13:4
Read only memory (ROM) B14 16 C13—19
Read/write head 23
Reals 189
Receive message routine CD9.1:6
Recursive procedures A26 29
Reduced Instruction Set Computer (RISC) CD2.19:4
Reduced instruction set computer (RISC), addressing modes and instruction formats D5—9
Reduced instruction set computer (RISC), Alpha D27—28
Reduced instruction set computer (RISC), architecture CD5.12:3
Reduced instruction set computer (RISC), ARM D36—38
Reduced instruction set computer (RISC), desktop versus embedded D3—5
Reduced instruction set computer (RISC), digital signal-processing extensions D19
Reduced instruction set computer (RISC), M32R D40—41
Reduced instruction set computer (RISC), MIPS D9—16 20—24
Reduced instruction set computer (RISC), MIPS16 D41—43
Reduced instruction set computer (RISC), MIPS64 D25—27
Reduced instruction set computer (RISC), multimedia extensions D16—19
Reduced instruction set computer (RISC), PA-RISC 2.0 D34—36
Reduced instruction set computer (RISC), PowrPC D32—33
Reduced instruction set computer (RISC), SPARCv.9 D29—32
Reduced instruction set computer (RISC), SuperH D39—40
Reduced instruction set computer (RISC), Thumb D38—39
Redundancy see RAID (redundant arrays of inexpensive disks)
Reference bit 519
refresh rate 18
Reg B21—22
Register addressing 100
Register file 293—294 B49 53—55
Register file, read 385 390 392 402
Register use conventions A22—33
Registers 52—53 59 88 290 532
Registers, allocation CD2.12:7—9
Registers, architectural 448
Registers, dedicated CD2.19:2
Registers, destination 64
Registers, general-purpose 135 138 CD2.19:2—3
Registers, global pointer 85
Registers, IA-32 137—138
Registers, jump 76 80
Registers, mapping into numbers 60—68
Registers, number 294
Registers, renaming 439
Registers, special-purpose CD2.19:2
registers, spilling 58 80
Relational databases CD8.11:4—5
Reliability 573
Relocation 513
Relocation information A13
Remainder 183
Remington-Rand CD1.7:4
Remote access times CD9.1:7
Reorder buffer 443
Reproducibility 255—256
Requested word first 482
Reservation stations 443
Response time 242 244
Restartable instruction 533
Restorations 572
Return address 80
ring topology CD9.6:27
| Rings CD7.9:7
Ripple carry B39 44—45
RISC see Reduced instruction set computer
Ritchie, Dennis CD2.19:7 CD7.9:8 11
Rotational delay 570
Rotational latency 570
Rounding 214—215 CD3.10:2—4
routers CD8.3:6
Sandisk Corp. 605
Scanning CD2.12:1
Scientific notation 189 191
Secondary memory 23
sectors 569
Seek 569
Seek time 569—570
Segmentation 514—515
Selector value B9
Selinger, Patricia CD8.11:5
Semantic analysis CD2.12:1
Semaphores CD9.3:18
Semiconductor 29
Send message routine CD9.1:6
Sensitivity list B24
Separate compilation A18
Sequential elements 290
Sequential logic B5 55—57
Servers 5
Set associative cache 497 504
set on less than 75 77 165 301
set on less than immediate 77 165
set on less than immediate unsigned 165 169
set on less than unsigned 165 169
Set-up time B53
Shadowing 575
Shared memory CD9.4:22 24
Shared virtual memory CD9.4:24
Shared-memory processors CD9.1:4—5
Shift amount 69
Shifts 69
Sign and magnitude 162 191
Sign bit 163
Sign extension 164 167—168 294 296
Signed division 187—188
Signed multiplication 180
Signed numbers 160—170
Significand 193
Silicon 29
Silicon crystal ingot 29
Silicon Graphics see MIPS
Simple programmable logic devices (SPLDs) B77
simplicity 285
Simputer 45
Simula-67 CD2.19:7
Simultaneous multithreading (SMT) CD9.7:31—34
Single address space multiprocessors CD9.1:4—6
Single bus, multiprocessors connected by a CD9.3:ll—20
Single instruction multiple data (SIMD) CD9.11:47—49 51
Single instruction single data (SISD) IMD 2.12 CD9.11:47
Single precision 192
Single-cycle implementation scheme 300—318
Single-cycle implementation scheme, pipelined performance versus 372—374
Small computer systems interface (SCSI) 573
Smalltalk CD2.19:7
Smith, Jim CD6.13:2
Snooping cache coherency CD9.3:13
Software, applications 11—12
Software, performance affected by 10
Software, systems 11
Software, third-party of shrink-wrap 5
sort, body for for loop 126—127
sort, code for the body of 124—126
sort, full procedure 127—128
sort, Java CD2.14:6—14
sort, passing parameters 127
sort, register allocation 123
Source language A6
SPARCv.9 D29—32
Spatial locality 468—469
SPEC (System Performance Evaluation Corp.), CPU benchmarks 254—255 259—266 CD4.7:2—3 IMD4:7—8
SPEC (System Performance Evaluation Corp.), file server benchmarks 599
SPEC (System Performance Evaluation Corp.), Web server benchmarks 599
SPEC ratio 259
speculation 434—435
SPECweb99 benchmark 262—266
Speedup IMD4:5
Spilling registers 58 80
Spilt caches 487
SPIM A40—45 CDA:l—2
SPIM, command-line options A42 CDA1—3
Spin waiting CD9.3:19 20
Split transaction protocol 585
SRAM see Static random access memory
SRT division 188
STACK 80
Stack, allocating space for data on 86
Stack, instructions CD2.19:3—4 IMD2:8—9
Stack, pointer 80
Stack, segment A22
Stale data problem 595
Stallman, Richard CD2.19:8
Standby spares 579
Stanford DASH multiprocessor CD9.11:52
State elements 289—290 B47—48
Static data segment 87 A20—22
Static multiple issue 433 435—442 CD6.13:4
Static random access memory (SRAM) 20 469 B57—60
static storage class 85
Stewart, Robert G. CD3.10:7
Sticky bit 215
Stone, Harold S. CD3.10:7
Stonebraker, Mike CD8.11:5
STOP 440
Storage classes, types of 85
Storage, disk 569—580 CD8.11:l—4
Storage, for digital cameras 603—606
STORE 57
Store buffer 445 485
store byte 91
store conditional CD9.3:19—20
store half 94
store word 57—59 294 300—318
Stored-program concept 49 215
Strength reduction 118
Stretch computer CD6.13:l—2
Strings, C 92—93
Strings, Java 93—95
Striping 575
Stroustrup, Bjarne CD2.19:7
Structural hazards 375
Structural specification B21
Structured Query Language (SQL) CD8.11:4—5
subroutines CD5.7:2
Subtract 49—51 301
subtract unsigned 172
Subtraction 170—176
Sum of products B10—12
Sun Microsystems CD4.7:2 CD7.9:9
Supercomputers, denned 5
Supercomputers, first CD1.7:5
SuperH D39—40
Superscalar processors 348 442—445 CD6.13:4
Supervisor process 529
swap, code for the body of 122—123
swap, full procedure 123
swap, Java CD2.14:6—14
swap, register allocation 122
Swap, space 517
switch statement 76
switched networks CD8.3:5
switches CD8.3:7
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