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| Patterson D.A., Hennessy J.L. — Computer Organization and Design: The Hardware/Software Interface |
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| Ïðåäìåòíûé óêàçàòåëü |
Hardware, functions of 15
Hardware, performance affected by 10
Hardware, synthesis tools B21
Hardwired control 348 CD5.12:2
Harvard Architecture CD 1.7:3
hazards see also Pipelining hazards
Hazards, detection unit 413—415
Heap, allocating space for data on 87—88
Heat sink 22
Held, Gerald CD8.11:5
Hewlett-Packard CD2.19:5 CD3.10:6—7 CD4.7:2
Hewlett-Packard, PA—RISC 2.0 D34—36
Hexadecimal-binary conversion table 62
HI 181
High-level optimization 116—117
High-level programming languages, advantages of 14 —15
High-level programming languages, architectures CD2.19:4
High-level programming languages, defined 13
High-level programming languages, translating into instructions that hardware can execute 12—15
Hit(s), Average Memory Access Time (AMAT) IMD7:1
Hit(s), denned 470
Hit(s), rate/ratio 470—471
Hit(s), time 471
Hitachi, SuperH D39—40
Hold time B53
Hot swapping 579
hubs CD8.3:7
I/O, buses 582
I/O, communicating with processor 590—591
I/O, designing a system 600—603
I/O, devices 15 566 A38—40
I/O, digital camera example 603—606
I/O, diversity of 568
I/O, fallacies and pitfalls 606—609
I/O, giving commands to devices 589—590
I/O, historical development of CD8.11:1—9
I/O, instructions 590
I/O, interfacing devices to processor, memory, and operating system 588—596
I/O, interrupt priority levels 591—593
I/O, interrupt-driven 590—591
I/O, measuring performance 567
I/O, memory-mapped 589—590
I/O, performance 597—600
I/O, rate 598
I/O, requests 568
I/O, transferring data between devices and memory 593—595
IBM, disk storage CD8.11:1—4
IBM, early computers CD1.7:5
IBM, floating points CD3.10:2 3—4
IBM, floppy disks CD1.7:6 CD8.11:2
IBM, history of programming languages CD2.19:6
IBM, microprogramming CD5.12:1—2
IBM, multiple issue CD6.13:4
IBM, PowrPC D32—33 IMD2:17—20 IMD3:10
IBM, RAID CD8.11:6
IBM, Stretch computer CD6.13:l—2
IBM, virtual memory CD7.9:5—7 10
IBM, Winchester disks CD8.11:2 4
IEEE 754 floation-point standard 193—196 CD3.10:7—9
If-then-else statements, compiling into conditional branches 72—73
Immediate addressing 100
implementation 22 24
Imprecise interrupts/exceptions 432 CD6.13:3
IMS CD8.11:4
In-order commit 445
In-order completion 445
Induction variable elimination 119—120
infinity 193
Ingres CD8.11:5
input devices 15 566 A38—40
Input don’t cares Â16
Input operation 582
Inputs, asynchronous Â75—77
Instruction decode 385 390 392 402
Instruction encoding, MIPS floating-point 208
Instruction fetch 385 388—389 392 400
Instruction format 61
Instruction group 440
Instruction latency 452
Instruction mix 253
Instruction register (ILP) 319 321
Instruction sets, addressing 95—105
Instruction sets, architecture 22 24
Instruction sets, compiler optimization 116—121
Instruction sets, decision-making instructions 72—74
Instruction sets, denned 48
Instruction sets, designing, for pipelining 374—375
Instruction sets, historical development of CD2.19:l—9
Instruction sets, logical operations 68—71
Instruction sets, operands of hardware 52—60
Instruction sets, operations of hardware 49—52
Instruction sets, representing instructions to computer 60—68
Instruction sets, styles IMD2:7—9
Instruction sets, supporting procedures 79—90
Instruction sets, to process text 90—95
Instruction sets, translating and starting a program 106—115
Instruction-level parallelism (ILP) CD9.7:33 433 CD6.13:5
Integers, signed versus unsigned 165
Integrated circuits (ICs), costs IMD1:1—2
Integrated circuits (ICs), denned 20 27—28
Integrated circuits (ICs), how they are manufactured 28—33
Integrated Data Store (IDS) CD8.11:4
Intel CD1.7:5 6 CD8.11:8 see
Intel 80286 135 CD2.19:5
Intel 80386 CD2.19:5
Intel 80486, 135 CD2.19:5
INTEL 8086 135 CD2.19:2 4 5
Intel 8087 135 CD3.10:7
Intel IA-32 59
Intel IA-32, addressing modes 138
Intel IA-32, complexity of 347—348
Intel IA-32, conclusions 142—143
Intel IA-32, fallacies and pitfalls 143—144
Intel IA-32, floating point 217—220
Intel IA-32, historical development of 134—137 CD2.19:4—5
Intel IA-32, instruction encoding 140—142
Intel IA-32, integer operations 138—140
Intel IA-32, registers 137—138
Intel IA-64 435 CD5.12:3
Intel IA-64, architecture 440—442 CD6.13:4—5
Intel iSC 860 and Paragon CD9.11:52
Intel Pentium and Pentium Pro 135 CD2.19:5 448—450
Intel SPEC CPU benchmarks 254—255 259—266
Intel SPECweb99 benchmark 262—266
Intel Streaming SIMD Extension 2 (SSE2) 136
Intel Streaming SIMD Extension 2 (SSE2), floating points 220
Intel Streaming SIMD Extensions (SSE) 135—136
Interface message processor (IMP) CD8.3:5
Interference graph CD2.12:7
Interleaving 489
Intermediate representation CD2.12:2—3
Internet CD8.11:7
Internet, news services 464—465
Internetworking CD 8.3:1—4
Interrupt-driven I/O 590—591
Interrupts 173 A33—38
Interrupts, handler A33
Interrupts, imprecise 432 CD6.13:3
Interrupts, priority levels 591—593
Interrupts, use of term 340—341
Intrinsity FastMATH processor example 485—487 524
Invalid operations 193
Issue packet 435
Issue slots 434
J-type 97
Java virtual machine (JVM) 115 CD2.14:3
Java, bytecode 114 CD2.14:1 2
Java, characters and strings 93—95
Java, compiling CD2.14:4—6
Java, development of CD2.19:7
| Java, interpreting CD2.14:l—3
Java, invoking methods CD2.14:6
Java, logical operations 68—71
Java, sort and swap CD2.14:6—13
Java, translating hierarchy 114—115
Java, while loop CD2.14:3—4 5—6
Jhai Foundation, PC network 44—45
Jobs, Steven CD1.7:5
Johnson, Reynold Â. CD8.11:1
Joy, Bill CD7.9:9
Jump 73 77 80 89 296
Jump address table 76 77 IMD2:15—16
jump register 76
jump, addressing in 97—99
jump, datapath and control and 313—314 321 328 336
jump-and-link 79—80 89
Just-in-Time (JTT) compiler 115
Kahan, William CD3.10:5—7 8 9
Kahn, Robert CD8.11:7
Karnaugh maps B18
Katz, Randy CD8.11:6
Kay, Alan CD2.19:7
Kernel benchmarks CD4.7:2 IMD4:7—8
Kernel process 529
Knuth, Donald CD2.19:8
Labels, external/global and local A11
Lampson, Butler CD7.9:8 11
Laptop computers, performance versus power versus energy efficiency 263—265
Latches B59—53
Latency, instruction 452
Latency, pipeline 383
Leaf procedures 83 93
Least recently used (LRU) 504 518 519
Least significant bit 161
Level-sensitive clocking B74—75
Link editor 109
Linkers 108—111 A4 18—19
LINPACK CD3.10:3 CD4.7:2
Linux 11 CD7.9:11
Liquid crystal displays (LCDs) 18
Lisp CD2.19:6
Little Endian 56 A43
Live range CD2.12:7
Livermore Loops CD4.7:2
lo 181
Load 54 57
Load, advanced 442
Load, byte 91 164
Load, byte unsigned 164
Load, half 94 164
Load, halfword unsigned 164
Load, linked CD9.3:19
Load, locked CD9.3:19
Load, upper immediate 95
Load, word 54 57 59 294 300—318
Load-use data hazard 377
Loader 112
Loading A19—20
Loading 32-bit constant 96
local area networks (LANs) 26 CD8.3:5—8 CD8.11:7—8
local labels A11
Local miss rate 509
Local optimization 117—121 CD2.12:3—4
Locality, principle of 468—469
LOCK CD9.1:5
Lock variables CD9.3:18
Logic design conventions 289—292
Logic, arrays of logic elements B18—19
Logic, combinational B5 8—20 23—25
Logic, equations B6—7 C12—13
Logic, sequential B5 55—57
Logic, two-level B10—14
Logical operations 68—71 B6 IMD2:21—22
Long instruction word (LEW) CD6.13:4
long-haul networks CD8.3:5
Lookup tables (LUTs) B78
Loops 74—75
Loops, branch 421—422
Loops, unrolling 117 438—440
Lorie, Raymond CD8.11:5
M32R D40—41
Machine code 61
Machine language 61 A3
Machine language, decoding 100—104
Machine language, MIPS floating-point 207
Machine language, object file and 108
MacOS 11
macros A4 15—17
Magnetic disks 23 569
Magnetic disks, differences between main memory and 24
Magnetic disks, memory hierarchies and 469 513
Magnetic resonance imaging (MRI) 622—623
Magnetic tape 25
Main memory 23
Main memory, differences between magnetic disks and 24
Make the common case fast 267 285
Mark machines CD 1.7:3
Mask 70
Mauchly, John CD1.7:1 2 4
McCarthy, John CD2.19:6 CD7.9:7 11
McKeeman, William CD2.19:8
Mealy machine 338 340 B68
Mealy, George 338
Mean time between failures (MTBF) 573
Mean time to failure (MTTF) 573 574 606
mean time to repair (MTTR) 573 574
Megabyte 23
Memories 290
Memory 8
Memory data register (MDR) 319 328
Memory elements, latches, flip-flops, and register files B49—57
Memory elements, SRAMs and DRAMs B57—67
Memory hierarchy, caches 473—511
Memory hierarchy, denned 469
Memory hierarchy, fallacies and pitfalls 550—552
Memory hierarchy, framework for 538—545
Memory hierarchy, historical development of CD7.9:5—7
Memory hierarchy, levels 470—471
Memory hierarchy, methods for building 469—470
Memory hierarchy, overall operation of 527—528
Memory hierarchy, Pentium P4 and AMD Opteron 546—550
Memory hierarchy, trends for 553—555
Memory hierarchy, virtual 511—538
Memory reference 327 328 334—335
memory, access 385 390 392 402
Memory, allocation 87—88
Memory, Average Memory Access Time (AMAT) IMD7:1
Memory, board 20
memory, cache 20
Memory, cards 25
Memory, consistency model CD9.3:15
Memory, defined 20 23
Memory, direct memory access (DMA) 594—596
Memory, distributed CD9.4:22 24
Memory, dynamic random access (DRAM) 20 469 487—488 490—491 513 B60 63—65
Memory, historical development of CD7.9:1—12
Memory, main 23
memory, mapping 512
Memory, nonvolatile 23
Memory, operands 54—55
Memory, primary 23
Memory, random access (RAM) 20
Memory, read only (ROM) B14 16 C13—19
Memory, secondary 23
Memory, shared CD9.1:4—5 CD9.4:22 24
Memory, static random access (SRAM) 20 469 B57—60
Memory, transferring data between devices and 593—595
Memory, unit 292
Memory, usage A20—22
Memory, virtual 511—538
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