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| Intel Corporation — IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide |
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| Предметный указатель |
SNaN, compatibility, IA-32 processors 18-10 18-16
Snooping mechanism 7-9 10-4
software interrupts 5-4
Software-controlled bus locking 7-4
Split pages 18-18
Spurious interrupt, local APIC 8-38
SS register, saving on call to exception or interrupt handler 5-15
SSE extensions, checking for support for FXSAVE and FXRSTOR instructions 12-2
SSE extensions, checking for with CPUID instruction 12-2
SSE extensions, designing facilities for automatic saving of SSE state 12-7
SSE extensions, EM flag 2-15
SSE extensions, emulation of 12-6
SSE extensions, initialization 9-9
SSE extensions, initializing 12-2
SSE extensions, introduction of into the IA-32 architecture 18-3
SSE extensions, providing exception handlers for 12-3 12-5
SSE extensions, providing operating system support for 12-1
SSE extensions, saving and restoring SSE and state 12-6
SSE extensions, saving SSE state on task or context switches 12-7
SSE extensions, SIMD Floating-point exception (#XF) 5-53
SSE extensions, system programming 12-1
SSE extensions, using TS flag to control saving of SSE state 12-8
SSE feature flag, CPUID instruction 9-9 12-2
SSE2 extensions, checking for support for FXSAVE and FXRSTOR instructions 12-2
SSE2 extensions, checking for with CPUID instruction 12-2
SSE2 extensions, designing facilities for automatic saving of SSE state 12-7
SSE2 extensions, EM flag 2-15
SSE2 extensions, emulation of 12-6
SSE2 extensions, initialization 9-9
SSE2 extensions, initializing 12-2
SSE2 extensions, introduction of into the IA-32 architecture 18-3
SSE2 extensions, providing exception handlers for 12-3 12-5
SSE2 extensions, providing operating system support for 12-1
SSE2 extensions, saving and restoring SSE and state 12-6
SSE2 extensions, saving SSE state on task or context switches 12-7
SSE2 extensions, SIMD Floating-point exception (#XF) 5-53
SSE2 extensions, system programming 12-1
SSE2 extensions, using TS flag to control saving of SSE state 12-8
SSE2 feature flag, CPUID instruction 9-9 12-2
Stack fault exception (#SS) 5-39 5-40
Stack fault, x87 FPU 18-9 18-15
Stack pointers privilege level 0, 1, and 2 stacks 6-6
Stack pointers, size of 3-12
Stack segments, paging of 2-5
Stack segments, privilege level checks when loading the SS register 4-12
Stack segments, size of stack pointer 3-12
Stack switching on call to exception or interrupt handler 5-15
Stack switching, inter-privilege level calls 4-21
Stack switching, masking exceptions and interrupts when switching stacks 5-10
Stack-fault exception (#SS) 18-36
Stacks, error code pushes 18-35
Stacks, faults 5-39 5-40
Stacks, for privilege levels 0 1 and
Stacks, interlevel RET/IRET from a 16-bit interrupt or call gate 18-35
Stacks, managment of control transfers for 16- and 32-bit procedure calls 17-5
Stacks, operation on pushes and pops 18-34
Stacks, pointers to in TSS 6-6
Stacks, stack switching 4-21
Stacks, usage on call to exception or interrupt handler 18-35
Stepping information, following processor initialization or reset 9-5
STI instruction 5-9
Store buffer in IA-32 processors 18-37
Store buffer, caching terminology 10-4
Store buffer, characteristics of 10-2
Store buffer, description of 10-3 10-22
Store buffer, location of 10-1
Store buffer, operation of 10-22
STPCLK# pin 5-4 15-22
STR instruction 2-20 3-17 6-9
Strong uncached (UC) memory type, description of 10-5
Strong uncached (UC) memory type, effect on memory ordering 7-12
Strong uncached (UC) memory type, use of 9-9 10-8
SUB instruction 7-5
Supervisor mode, description of 4-32
Supervisor mode, U/S (user/supervisor) flag 4-32
SVR (spurious-interrupt vector register), local APIC 8-10 18-28
SYSENTER instruction 3-9 4-12 4-13 4-25
SYSENTER_CS_MSR 4-25
SYSENTER_EIP_MSR 4-25
SYSENTER_ESP_MSR 4-25
SYSEXIT instruction 3-9 4-12 4-13 4-25
System programming, MMX technology 11-1
System programming, SSE and SSE extensions 12-1
System, architecture 2-1 2-2
System, data structures 2-2
System, instructions 2-6 2-18
System, registers, introduction to 2-5
System, segment descriptor, layout of 4-3
System, segments, paging of 2-5
System-management mode see "SMM"
T (debug trap) flag 6-6
T (debug trap) flag, TSS 6-6 15-1
Task gates, descriptor 6-9
Task gates, executing a task 6-3
Task gates, handling a virtual-8086 mode interrupt or exception through 16-20
Task gates, in IDT 5-12
Task gates, introduction to 2-3 2-4
Task gates, layout of 5-12
Task gates, referencing of TSS descriptor 5-18
Task management 6-1
Task management, data structures 6-4
Task management, mechanism, description of 6-3
Task register 3-17
Task register, description of 2-11 6-1 6-8
Task register, initializing 9-13
Task register, introduction to 2-5
Task State Segment see "TSS"
Task switches, saving MMX state on 11-5
Task switching, description of 6-3
Task switching, exception condition 15-10
Task switching, operation 6-13
Task switching, preventing recursive task switching 6-17
Task switching, saving SSE and SSE2 state on task or context switches 12-7
Tasks, address space 6-18
Tasks, description of 6-1
Tasks, exception-handler task 5-14
Tasks, executing 6-3
Tasks, Intel 286 processor tasks 18-41
Tasks, interrupt-handler task 5-14
Tasks, interrupts and exceptions 5-18
tasks, linking 6-16
Tasks, logical address space 6-20
Tasks, management 6-1
Tasks, mapping to linear and physical address spaces 6-19
Tasks, restart following an exception or interrupt 5-6
Tasks, state (context) 6-2 6-3
Tasks, structure 6-1
Tasks, switching 6-3
Tasks, task management data structures 6-4
Test registers 18-24
TF (trap) flag, EFLAGS register 2-8 5-17 13-10 15-1 15-10 15-12 15-15 15-20 16-6 16-26
Thermal monitoring, automatic 13-19
Thermal monitoring, catastrophic shutdown detector 13-19
Thermal monitoring, detection and measurement of over-temperature conditions 13-23
Thermal monitoring, detection of thermal monitor and software controlled clock modulation facilities 13-22
Thermal monitoring, overview of 13-18
Thermal monitoring, software controlled clock modulation 13-21
Thermal monitoring, stop clock mechanism 13-18
Thermal monitoring, usage models 13-22
Thermal sensor, automatic thermal monitor 13-19
Thermal sensor, catastrophic shutdown detector 13-19
Thermal sensor, interrupt 8-2
Time-stamp counter, description of 15-22
Time-stamp counter, reading 2-22
Time-stamp counter, software drivers for 15-61
Timer, local APIC 8-20
Tl (table indicator) flag, segment selector 3-7
TLBs, description of 3-18 10-1 10-3
TLBs, flushing 10-21
TLBs, invalidating (flushing) 2-21
| TLBs, relationship to PGE flag 3-27 18-22
TLBs, relationship to PSE flag 3-22 10-21
TLBshootdown 7-13
TM flag, CPUID instruction 13-22
TMR (Trigger Mode Register), local APIC 8-36
TR (trace message enable) flag, DebugCtlMSR MSR 15-13 15-20
Trace cache 10-3
Transcendental instruction accuracy 18-8 18-17
Translation lookaside buffer see "TLB"
Trap gates for 16-bit and 32-bit code modules 17-2
Trap gates in IDT 5-12
Trap gates, difference between interrupt and trap gates 5-17
Trap gates, handling a virtual-8086 mode interrupt or exception through 16-17
Trap gates, introduction to 2-3 2-4
Trap gates, layout of 5-12
Traps, description of 5-6
Traps, restarting a program or task after 5-7
TS (task switched) flag, CR0 control register 2-14 2-20 5-30 6-14 11-1 12-3 12-8
TSD (time-stamp counter disable) flag, CR4 control register 2-16 4-27 15-22 18-21
TSS descriptor, B (busy) flag 6-7
TSS descriptor, initialization for multitasking 9-13
TSS descriptor, structure of 6-7
TSS segment selector, field, task-gate descriptor 6-9
TSS segment selector, writes 18-29
TSS, 16-bit TSS, structure of 6-21
TSS, 32-bit TSS, structure of 6-4
TSS, CR3 control register (PDBR) 6-5 6-18
TSS, description of 2-3 2-4 6-1 6-4
TSS, EFLAGS register 6-6
TSS, EIP 6-6
TSS, executing a task 6-3
TSS, floating-point save area 18-14
TSS, general-purpose registers 6-5
TSS, I/O map base address field 6-6 18-30
TSS, I/O permission bit map 6-6
TSS, initialization for multitasking 9-13
TSS, invalid TSS exception 5-35 5-36
TSS, LDT segment selector field 6-6 6-18
TSS, link field 5-18
TSS, order of reads/writes to 18-29
TSS, page-directory base address (PDBR) 3-23
TSS, pointed to by task-gate descriptor 6-9
TSS, previous task link field 6-6 6-16 6-18
TSS, privilege-level 0, 1, and 2 stacks 4-22
TSS, referenced by task gate 5-18
TSS, segment registers 6-6
TSS, T (debug trap) flag 6-6
TSS, task register 6-8
TSS, using 16-bit TSSs in a 32-bit environment 18-30
TSS, virtual-mode extensions 18-29
type checking 4-6
Type field, IA32_MTRR_DEF_TYPE MSR 10-25
Type field, IA32_MTRR_PHYSBASEn MTRR 10-28
Type field, segment descriptor 3-11 3-13 3-15 4-2 4-6
Type of segment 4-6
U/S (user/supervisor) flag, page-directory entry 4-2 4-3 4-32
U/S (user/supervisor) flag, page-table entries 3-26 16-11
U/S (user/supervisor) flag, page-table entry 4-2 4-3 4-32
UC-(uncacheable) memory type 10-5
UD2 instruction 5-28 18-4
Un-normal number 18-10
Uncached (UC) memory type see "Strong uncached (UC) memory type"
Uncached (UC-) memory type 10-8
Undefined opcodes 18-5
Unit mask field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-59
User mode, description of 4-32
User mode, U/S (user/supervisor) flag 4-32
User-defined interrupts 5-2 5-56
USR (user mode) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-59
V (valid) flag, IA32_MTRR_PHYSMASKn MTRR 10-28
Variable-range MTRRs, description of 10-27
VCNT (variable range registers count) field, IA32_MTRRCAP MSR 10-24
Vector see "Interrupt vector"
Vectors exceptions 5-2
Vectors interrupts 5-2
Vectors reserved 8-34
VERR instruction 2-21 4-28
VERW instruction 2-21 4-28
VIF (virtual interrupt) flag, EFLAGS register 2-9 2-10 18-6
VIP (virtual interrupt pending) flag, EFLAGS register 2-9 2-10 18-6
Virtual memory 2-5 3-1 3-2 3-17
Virtual-8086 mode, 8086 emulation 16-1
Virtual-8086 mode, description of 16-7
Virtual-8086 mode, emulating 8086 operating system calls 16-25
Virtual-8086 mode, enabling 16-8
Virtual-8086 mode, entering 16-11
Virtual-8086 mode, exception and interrupt handling, overview 16-15
Virtual-8086 mode, exceptions and interrupts, handling through a task gate 16-19
Virtual-8086 mode, exceptions and interrupts, handling through a trap or interrupt gate 16-17
Virtual-8086 mode, handling exceptions and interrupts through a task gate 16-20
Virtual-8086 mode, interrupts 16-8
Virtual-8086 mode, introduction to 2-7
Virtual-8086 mode, IOPL sensitive instructions 16-14
Virtual-8086 mode, l/O-port-mapped I/O 16-14
Virtual-8086 mode, leaving 16-12
Virtual-8086 mode, memory mapped I/O 16-15
Virtual-8086 mode, native 16-bit mode 17-1
Virtual-8086 mode, overview of 16-1
Virtual-8086 mode, paging of virtual-8086 tasks 16-10
Virtual-8086 mode, protection within a virtual-8086 task 16-11
Virtual-8086 mode, special I/O buffers 16-15
Virtual-8086 mode, structure of a virtual-8086 task 16-9
Virtual-8086 mode, virtual I/O 16-14
Virtual-8086 mode, VM flag, EFLAGS register 2-9
Virtual-8086 tasks, paging of 16-10
Virtual-8086 tasks, protection within 16-11
Virtual-8086 tasks, structure of 16-9
VM (virtual-8086 mode) flag, EFLAGS register 2-7 2-9
VME (virtual-8086 mode extensions) flag, CR4 control register 2-9 2-10 2-16 18-21
WAIT/FWAIT instructions 5-30 18-8 18-18
WB (write back) memory type 10-6 10-8
WB (write-back) pin (Pentium processor) 10-14
WB/WT# pins 10-14
WBINVD instruction 2-21 4-26 7-14 10-17 10-18 10-19 18-4
WC (write combining) flag, IA32_MTRRCAP MSR 10-25
WC (write combining), memory type 10-6 10-8
WC buffer see "Write combining (WC) buffer"
WP (write protect) flag, CR0 control register 2-13 4-33 18-21
WP (write protected) memory type 10-6
Write back (WB) memory type 7-12
Write combining (WC) buffer 10-2 10-7
Write, forwarding 7-9
Write, hit 10-4
Write-back caching 10-5
WRMSR instruction 2-22 2-23 4-26 7-14 15-12 15-19 15-23 15-30 15-58 15-60 15-62 18-4 18-39
WT (write through) memory type 10-6 10-8
WT# (write-through) pin (Pentium processor) 10-14
x87 FPU control word compatibility, IA-32 processors 18-9
x87 FPU floating-point error exception (#MF) 5-47 5-48
x87 FPU status word condition code flags 18-8
x87 FPU tag word 18-9
x87 FPU, configuring thex87 FPU environment 9-6
x87 FPU, device-not-available exception 5-30 5-31
x87 FPU, effect of MMX instructions on pending x87 floating-point exceptions 11-6
x87 FPU, effects of MMX instructions on x87 FPU state 11-3
x87 FPU, effects of MMX, x87 FPU, FXSAVE, and FXRSTOR instructions on x87 FPU tag word 11-3
x87 FPU, error signals 18-12
x87 FPU, initialization 9-6
x87 FPU, instruction synchronization 18-18
x87 FPU, register stack, aliasing with MMX registers 11-2
x87 FPU, setting up for software emulation of x87 FPU functions 9-7
x87 FPU, using in SMM 13-12
x87 FPU, using TS flag to control saving of x87 FPU state 12-8
x87 FPU, x87 floating-point error exception (#MF) 5-47
x87 FPU, x87 FPU, compatibility with IA-32 x87 FPUs and math coprocessors 18-7
XADD instruction 7-4 18-4
xAPIC, communication through system bus 8-5
xAPIC, determining lowest priorty processor 8-30
xAPIC, interrupt control register 8-25
xAPIC, introduction to 8-5
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