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| Intel Corporation — IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide |
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| Предметный указатель |
Local vector table (LVT), description of 8-15
Local vector table (LVT), thermal entry 13-20
LOCK prefix 2-22 5-28 7-2 7-3 7-4 7-11 18-38
LOCK# signal 2-22 7-2 7-3 7-5 7-7
Locked (atomic) operations on IA-32 processors 18-38
Locked (atomic) operations, automatic bus locking 7-4
Locked (atomic) operations, bus locking 7-3
Locked (atomic) operations, effects of a locked operation on internal processor caches 7-7
Locked (atomic) operations, loading a segment descriptor 18-23
Locked (atomic) operations, overview of 7-2
Locked (atomic) operations, software-controlled bus locking 7-4
Logical address space, of task 6-20
Logical address, description of 3-6
Logical destination mode, local APIC 8-28
LSL instruction 2-21 4-29
LSS instruction 3-9 4-10
LTR instruction 2-20 4-26 6-9 7-14 9-13
LVT see "Local vector table"
Machine-check architecture, availability of machine-check architecture and exception 14-10
Machine-check architecture, compatibility with Pentium processor implementation 14-1
Machine-check architecture, error codes, compound 14-12
Machine-check architecture, error codes, interpreting 14-11
Machine-check architecture, error codes, simple 14-11
Machine-check architecture, error-reporting MSRs 14-5
Machine-check architecture, first introduced 18-26
Machine-check architecture, global MSRs 14-2
Machine-check architecture, guidelines for writing machine-check software 14-14
Machine-check architecture, IA32_MCG extended machine check state MSRs 14-8
Machine-check architecture, initialization of 14-10
Machine-check architecture, interpreting error codes, example (P6 family processors) E-1 F-1
Machine-check architecture, introduction of in IA-32 processors 18-40
Machine-check architecture, logging correctable machine-check errors 14-17
Machine-check architecture, machine-check error codes, external bus errors 14-14
Machine-check architecture, machine-check exception handler 14-15
Machine-check architecture, MSRs 14-2
Machine-check architecture, overview 14-1
Machine-check architecture, Pentium processor machine-check exception handling 14-17
Machine-check architecture, Pentium processor style error reporting 14-9
Machine-check exception (#MC) 5-51 5-52 14-1 14-10 14-15 18-25 18-40
Maskable hardware interrupts, description of 5-4
Maskable hardware interrupts, handling with virtual interrupt mechanism 16-20
Maskable hardware interrupts, masking 2-8 5-8
MCA (machine-check architecture) flag, CPUID instruction 14-10
MCE (machine-check enable) flag, CR4 control register 2-17 18-21
MCE (machine-check exception) flag, CPUID instruction 14-10
MCG_CAP MSR 14-2 14-3
MCG_CTL MSR 14-5
MCG_STATUS MSR 14-4
MCi_ADDR MSR 14-7
MCi_CTL MSR 14-5
MCi_CTL MSRs 14-5
MCi_MISC MSR 14-8
MCi_STATUS MSR 14-6
MDA (message destination address), local APIC 8-28
Memory 10-1
Memory management, introduction to 2-5
Memory management, overview 3-1
Memory management, paging 3-1 3-2 3-17
Memory management, registers 2-10
Memory management, segments 3-1 3-2 3-3 3-7
Memory management, virtual memory 3-17
Memory ordering in IA-32 processors 18-37
Memory ordering out of order stores for string operations 7-10
Memory ordering, overview 7-7
Memory ordering, processor ordering 7-7
Memory ordering, snooping mechanism 7-9
Memory ordering, strengthening or weakening 7-11
Memory ordering, write forwarding 7-9
Memory ordering, write ordering 7-7
Memory type range registers see "MTRRs"
Memory types, caching methods, defined 10-5
Memory types, choosing 10-8
Memory types, MTRR types 10-23
Memory types, selecting for Pentium Pro and Pentium II processors 10-15
Memory types, selecting for Pentiumlll and Pentium 4 processors 10-16
Memory types, UC (strong uncacheable) 10-5
Memory types, UC- (uncacheable) 10-5
Memory types, WB (write back) 10-6
Memory types, WC (write combining) 10-6
Memory types, WP (write protected) 10-6
Memory types, writing values across pages with different memory types 10-17
Memory types, WT (write through) 10-6
MemTypeGet() function 10-32
MemTypeSet() function 10-34
MESI cache protocol 10-4 10-9
MFENCE instruction 2-14 7-8 7-11 7-12 7-14
Microcode update facilities, function 00H presence test 9-43
Microcode update facilities, function 01H write microcode update data 9-43
Microcode update facilities, function 02H microcode update control 9-47
Microcode update facilities, function 03H read microcode update data 9-48
Microcode update facilities, INT 15H-based interface 9-42
Microcode update facilities, microcode update 9-31
Microcode update facilities, microcode update loader 9-34
Microcode update facilities, microcode update specifications 9-38
Microcode update facilities, overview 9-31
Microcode update facilities, return codes 9-49
Microcode update facilities, update signature and verification 9-36
Mixing 16-bit and 32-bit code in IA-32 processors 18-35
Mixing 16-bit and 32-bit code overview 17-1
MMX technology, debugging MMX code 11-6
MMX technology, effect of MMX instructions on pending x87, floating-point exceptions 11-6
MMX technology, emulation of the MMX instruction set 11-1
MMX technology, exceptions that can occur when executing MMX instructions 11-1
MMX technology, introduction of into the IA-32 architecture 18-3
MMX technology, MMX register aliasing 11-1
MMX technology, MMX state 11-1
MMX technology, MMX state, saving and restoring 11-4
MMX technology, MMX state, saving on task or context switches 11-5
MMX technology, system programming 11-1
MMX technology, using TS flag to control saving of MMX state 12-8
Mode switching between real-address and protected mode 9-13
Mode switching to SMM 13-2
Mode switching, example 9-16
Model and stepping information, following processor initialization or reset 9-5
Model-specific registers see "MSRs"
modes of operation see "Operating modes"
MOV (control registers) instructions 2-20 4-26 7-14 9-14
MOV (debug registers) instructions 2-21 4-26 7-14 15-9
MOV instruction 3-9 4-10
MOVNTDQ instruction 7-8 10-4 10-19
MOVNTI instruction 2-14 7-8 10-4 10-19
MOVNTPD instruction 7-8 10-4 10-19
MOVNTPS instruction 7-8 10-4 10-19
MOVNTQ instruction 7-8 10-4 10-19
MP (monitor coprocessor) flag, CR0 control register 2-14 2-16 5-30 9-6 9-7 11-1 12-3
MP (monitor coprocessor) flag, CR0 register 18-8
MSR supported by B-16
MSRs, architectural B-26
MSRs, description of 9-8
MSRs, introduction of in IA-32 processors 18-39
MSRs, introduction to 2-5
MSRs, list of B-1
MSRs, machine-check architecture 14-2
MSRs, P6 family processors B-16
MSRs, Pentium 4 processor B-1
MSRs, Pentium processors B-25
MSRs, reading and writing 2-23
MSR_ TC_PRECISE_EVENT MSR A-30
MSR_EBC_FREQUENCY_ID MSR B-4
MSR_EBC_HARD_POWERON MSR B-2
MSR_EBC_SOFT_POWERON MSR B-3
MSR_LASTBRANCH_0 MSR B-9 15-12 15-13
MSR_LASTBRANCH_1 MSR B-9 15-12 15-13
MSR_LASTBRANCH_2 MSR B-9 15-12 15-13
MSR_LASTBRANCH_3 MSR B-9 15-12 15-13
MSR_LASTBRANCH_TOS B-9
MSR_LASTBRANCH_TOS MSR 15-12 15-13
MSR_LER_FROM_LIP MSR 15-16 B-8
MSR_LER_TO_LIP MSR 15-16 B-9
MSR_PEBS_ MATRIX_VERT MSR A-32
| MSR_PEBS_MATRIX_VERT MSR B-14
MTRR feature flag, CPUID instruction 10-24
MTRRcap MSR 10-24
MTRRfix MSR 10-27
MTRRs 7-11
MTRRs, address mapping for fixed-range MTRRs 10-27
MTRRs, cache control 10-14
MTRRs, description of 9-9 10-22
MTRRs, enabling caching 9-8
MTRRs, example of base and mask calculations 10-29
MTRRs, feature identification 10-24
MTRRs, fixed-range registers 10-26
MTRRs, IA32_MTRRCAP MSR 10-24
MTRRs, IA32_MTRR_DEF_TYPE MSR 10-25
MTRRs, initialization of 10-31
MTRRs, introduction of in IA-32 processors 18-40
MTRRs, introduction to 2-5
MTRRs, large page size considerations 10-37
MTRRs, mapping physical memory with 10-24
MTRRs, memory types and their properties 10-23
MTRRs, MemTypeGet() function 10-32
MTRRs, MemTypeSet() function 10-34
MTRRs, multiple-processor considerations 10-35
MTRRs, precedence of cache controls 10-14
MTRRs, precedences 10-31
MTRRs, programming interface 10-32
MTRRs, remapping memory types 10-31
MTRRs, state of following a hardware reset 10-23
MTRRs, variable-range registers 10-27
Multiple-processor initialization, MP protocol 7-15
Multiple-processor initialization, procedure C-2
Multiple-processor management, bus locking 7-3
Multiple-processor management, guaranteed atomic operations 7-3
Multiple-processor management, local APIC 8-1
Multiple-processor management, memory ordering 7-7
Multiple-processor management, MP protocol 7-15
Multiple-processor management, overview of 7-1
Multiple-processor management, propagation of page table and page directory entry changes 7-13
Multiple-processor management, SMM considerations 13-17
Multiple-processor system, relationship of local and I/O APICs, P6 family processors 8-4
Multiple-processor system, relationship of local and I/O APICs, Pentium 4 processor 8-4
Multisegment model 3-5
Multitasking, initialization for 9-13
Multitasking, linking tasks 6-16
Multitasking, mechanism, description of 6-3
Multitasking, overview 6-1
Multitasking, setting up TSS 9-13
Multitasking, setting up TSS descriptor 9-13
MXCSR register 5-53 9-10 12-6
NaN, compatibility, IA-32 processors 18-10
NE (numeric error) flag, CR0 control register 2-14 5-47 9-6 9-7 18-21
NE (numeric error) flag, CR0 register 18-8
NEG instruction 7-5
NetBurst micro-architecture see "Intel NetBurst micro-architecture"
NMI interrupt 2-22 8-5
NMI interrupt, description of 5-2
NMI interrupt, handling during initialization 9-10
NMI interrupt, handling in SMM 13-11
NMI interrupt, handling multiple NMIs 5-8
NMI interrupt, masking 18-27
NMI interrupt, receiving when processor is shutdown 5-33
NMI interrupt, reference information 5-24
NMI interrupt, vector 5-2
NMI# pin 5-2 5-24
Non-precise event-based sampling, defined 15-27
Non-precise event-based sampling, used for at-retirment counting 15-45
Non-precise event-based sampling, writing an interrupt service routine for 15-18
Non-retirement events 15-26 A-1
Nonconforming code segments, accessing 4-14
Nonconforming code segments, C (conforming) flag 4-14
Nonconforming code segments, description of 3-14
Nonmaskable interrupt see "NMI"
NOT instruction 7-5
Notation, bit and byte order 1-6
Notation, conventions 1-6
Notation, exceptions 1-9
Notation, hexadecimal and binary numbers 1-8
Notation, instruction operands 1-7
Notation, reserved bits 1-6
Notation, segmented addressing 1-8
NT (nested task) flag, EFLAGS register 2-9 6-12 6-13 6-16
Null segment selector, checking for 4-7
Numeric overflow exception (#O) 18-11
Numeric underflow exception (#U) 18-11
NV (invert) flag, PerfEvtSel0 MSR (P6 family processors) 15-60
NW (not write-through) flag, CR0 control register 2-13 9-8 10-12 10-13 10-17 10-35 10-36 18-22 18-23 18-31
Obsolete, instructions 18-5 18-18
OF flag, EFLAGS register 5-26
Opcodes undefined 18-5
Operands, instruction 1-7
Operands, operand-size prefix 17-2
Operating modes, introduction to 2-6
Operating modes, protected mode 2-6
Operating modes, SMM (system management mode) 2-6
Operating modes, virtual-8086 mode 2-7
OR instruction 7-5
OS (operating system mode) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-59
OSFXSR (FXSAVE/FXRSTOR support) flag, CR4 control register 2-17 9-9 12-2
OSXMMEXCPT (SIMD floating-point exception support) flag, CR4 control register 2-18 5-53 9-9 12-2
OUT instruction 7-11
OUTS instruction 15-9
Overflow exception (#OF) 5-26
P (present) flag, page-directory entry 5-44
P (present) flag, page-table entries 3-25
P (present) flag, page-table entry 5-44
P (segment-present) flag, segment descriptor 3-11
P5_MC_ADDR MSR 14-9 14-17 B-16 B-25
P5_MC_TYPE MSR 14-9 14-17 B-16 B-25
P6 family processors, compatibility with floating-point, software 18-7
P6 family processors, description of 1-1
P6 family processors, list of performance-monitoring events A-38
PAE (physical address extension) flag, CR4 control register 2-17 3-6 3-18 3-28 3-34 18-21 18-22
PAE feature flag, CPUID instruction 3-28
Page attribute table (PAT), compatibility with earlier IA-32 processors 10-41
Page attribute table (PAT), detecting support for 10-38
Page attribute table (PAT), IA32_CR_PAT MSR 10-38
Page attribute table (PAT), introduction to 10-37
Page attribute table (PAT), memory types that can be encoded with 10-39
Page attribute table (PAT), MSR 10-14
Page attribute table (PAT), precedence of cache controls 10-14
Page attribute table (PAT), programming 10-40
Page attribute table (PAT), selecting a memory type with 10-39
Page base address field, page-table entries 3-23 3-35
Page directory, base address 3-23
Page directory, base address (PDBR) 6-6
Page directory, description of 3-19
Page directory, introduction to 2-5
Page directory, overview 3-2
Page directory, setting up during initialization 9-13
Page frame see "Page"
Page tables, description of 3-19
Page tables, introduction to 2-5
Page tables, overview 3-2
Page tables, setting up during initialization 9-13
Page-directory entries 3-19 3-23 3-24 3-25 3-33 3-35 7-4 10-3
Page-directory-pointer (PDPTR) table 3-28
Page-directory-pointer-table entries 3-33
Page-fault exception (#PF) 3-18 5-44 5-45 5-46 18-26
Page-table base address field, page directory entries 3-23 3-35
Page-table entries 3-19 3-23 3-24 3-33 7-4 10-3 10-20
Pages, descripiton of 3-19
Pages, disabling protection of 4-2
Pages, enabling protection of 4-2
Pages, introduction to 2-5
Pages, overview 3-2
Pages, PG flag, CR0 control register 4-2
Pages, sizes 3-20
Pages, split 18-18
Paging, 32-bit physical addressing 3-20
Paging, 36-bit physical addressing, using PAE paging mechanism 3-28
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