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| Intel Corporation — IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide |
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| Предметный указатель |
IA32_MCi_ADDR MSR 14-7 B-14
IA32_MCi_ADDR MSRs 14-18
IA32_MCi_CTL MSR 14-5 B-14
IA32_MCi_MISC MSR 14-8 B-14
IA32_MCi_MISC MSRs 14-18
IA32_MCi_STATUS MSR 14-6 B-14
IA32_MCi_STATUS MSRs 14-15 14-18
IA32_MISC_ENABLE MSR 13-19 15-11 15-24 15-34 B-7
IA32_MTRRCAP MSR 10-24 10-25 B-4
IA32_MTRR_DEF_TYPE MSR 10-25
IA32_MTRR_FIXn, fixed ranger MTRRs 10-26
IA32_MTRR_PHYSBASEn (variable range) MTRRs 10-27
IA32_MTRR_PHYSMASKn (variable range) MTRRs 10-27
IA32_P5_MC_ADDR MSR B-1
IA32_P5_MC_TYPE MSR B-1
IA32_PAT_CR MSR 10-38
IA32_PEBS_ ENABLE MSR A-32
IA32_PEBS_ENABLE MSR 15-24 15-48 B-13
IA32_PLATFORM_ID B-1 B-16
IA32_STATUS MSR B-5
IA32_SYSENTER_CS MSR B-4
IA32_SYSENTER_EIP MSR B-4
IA32_SYSENTER_ESP MSR B-4
IA32_THERM_CONTROL MSR 13-21 13-22 B-7
IA32_THERM_INTERRUPT MSR 13-20 13-22 B-7
IA32_THERM_STATUS MSR 13-22 13-23 B-7
IA32_TIME_STAMP_COUNTER MSR B-1
ID (identification) flag, EFLAGS register 2-10 18-6
IDIV instruction 5-22 18-26
IDT, calling interrupt- and exception- handlers from 5-14
IDT, changing base and limit in real-address mode 16-6
IDT, description of 5-11
IDT, handling NMI interrrupts during initialization 9-10
IDT, initializing, for protected-mode operation 9-12
IDT, initializing, for real-address mode operation 9-10
IDT, introduction to 2-4
IDT, limit 18-27
IDT, paging of 2-5
IDT, structure in real-address mode 16-7
IDT, task switching 6-12
IDT, task-gate descriptor 6-9
IDT, types of descriptors allowed 5-12
IDT, use in real-address mode 16-6
IDTR register, description of 2-11 5-12
IDTR register, introduction to 2-4
IDTR register, limit 4-5
IDTR register, loading in real-address mode 16-6
IDTR register, storing 3-17
IE (invalid operation exception) flag, x87 FPU status word 18-9
IEEE Standard 754 for Binary Floating-Point Arithmetic 18-9 18-10 18-11 18-14 18-15 18-16 18-17
IF (interrupt enable) flag, EFLAGS register 2-8 2-9 5-8 5-13 5-17 13-10 16-6 16-26
IN instruction 7-11 18-38
INC instruction 7-5
Index field, segment selector 3-7
INIT interrupt 8-5
INIT# pin 5-4 9-2
INIT# signal 2-22
Initial-count register, local APIC 8-20
Initialization, built-in self-test (BIST) 9-1 9-2
Initialization, CS register state following 9-6
Initialization, EIP register state following 9-6
Initialization, example 9-16
Initialization, first instruction executed 9-6
Initialization, hardware reset 9-1
Initialization, IDT, protected mode 9-12
Initialization, IDT, real-address mode 9-10
Initialization, Intel 486 SX processor and Intel 487 SX math coprocessor 18-19
Initialization, location of software-initialization code 9-6
Initialization, model and stepping information 9-5
Initialization, multiple-processor (MP) bootup sequence for P6 family processors C-1
Initialization, multitasking environment 9-13
Initialization, overview 9-1
Initialization, paging 9-12
Initialization, processor state after reset 9-2
Initialization, protected mode 9-11
Initialization, real-address mode 9-10
Initialization, RESET# pin 9-1
Initialization, settingupexception-andinterrupt-handlingfacilities 9-12
Initialization, x87 FPU 9-6
Input/Output see "I/O"
INS instruction 15-9
Instruction operands 1-7
Instruction set, new instructions 18-4
Instruction set, obsolete instructions 18-5
Instruction-breakpoint exception condition 15-8
Instructions, privileged 4-26
Instructions, serializing 18-18
Instructions, supported in real-address mode 16-4
Instructions, system 2-6 2-18
INT (APIC interrupt enable) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-59
INT 3 instruction 2-4 5-25 15-2
INT instruction 2-4 4-12
INT n instruction 3-9 5-1 5-4 5-5
INT3 instruction 3-9 5-5
Intel 286 processor 18-7
Intel 287 math coprocessor 18-7
Intel 386 DX processor 18-7
Intel 386 SL processor 2-6
Intel 387 math coprocessor system 18-7
Intel 486 DX processor 18-7
Intel 486 SX processor 18-7 18-19
Intel 487 SX math coprocessor 18-7 18-19
Intel 8086 processor 18-7
Intel NetBurst micro-architecture 1-1
Intel Xeon processor 1-1
Intel Xeon processor MP, implementation of Hyper-Threading, technology in 7-23
Intel Xeon processor, implementation of Hyper-Threading technology in later, steppings of 7-23
Inter-processor interrupts (IPIs) 8-2
Interprivilege level calls, call mechanism 4-18
Interprivilege level calls, stack switching 4-21
Interprocessor interrupt (IPI) in MP systems 8-1
Interrupt command register (ICR), local APIC 8-21
Interrupt destination 8-31
Interrupt gates for 16-bit and 32-bit code modules 17-2
Interrupt gates in IDT 5-12
Interrupt gates, 16-bit, interlevel return from 18-35
Interrupt gates, clearing IF flag 5-9 5-17
Interrupt gates, difference between interrupt and trap gates 5-17
Interrupt gates, handling a virtual-8086 mode interrupt or exception through 16-17
Interrupt gates, introduction to 2-3 2-4
Interrupt gates, layout of 5-12
Interrupt handler, calling 5-14
Interrupt handler, defined 5-1
Interrupt handler, flag usage by handler procedure 5-17
Interrupt handler, procedures 5-14
Interrupt handler, protection of handler procedures 5-16
Interrupt handler, task 5-18 6-3
Interrupt, description of 5-1
Interrupts, APIC priority levels 8-34
Interrupts, automatic bus locking when acknowledging 18-38
Interrupts, control transfers between 16- and 32-bit code modules 17-8
Interrupts, description of 2-4 5-1
Interrupts, distribution mechanism, local APIC 8-29
Interrupts, enabling and disabling 5-8
Interrupts, handling 5-14
Interrupts, handling in real-address mode 16-6
Interrupts, handling in SMM 13-10
Interrupts, handling in virtual-8086 mode 16-15
Interrupts, handling multiple NMIs 5-8
Interrupts, handling through a task gate in virtual-8086 mode 16-20
Interrupts, handling through a trap or interrupt gate in virtual-8086 mode 16-17
Interrupts, IDT 5-11
Interrupts, IDTR 2-11
Interrupts, initializing for protected-mode operation 9-12
Interrupts, interrupt descriptor table see "IDT"
Interrupts, interrupt descriptor table register see "IDTR"
Interrupts, list of 5-3 16-8
Interrupts, local APIC 8-1
Interrupts, maskable hardware interrupts 2-8
Interrupts, masking maskable hardware interrupts 5-8
| Interrupts, masking when switching stack segments 5-10
Interrupts, overview of 5-1
Interrupts, priorities among simultaneous exceptions and interrupts 5-10
Interrupts, priority 8-34
Interrupts, propagation delay 18-27
Interrupts, real-address mode 16-8
Interrupts, restarting a task or program 5-6
Interrupts, software 5-56
Interrupts, sources of 8-2
Interrupts, summary of 5-3
Interrupts, user defined 5-2 5-56
Interrupts, valid APIC interrupts 8-18
Interrupts, vectors 5-2
Interrupts, virtual-8086 mode 16-8
INTn instruction 15-10
INTO instruction 2-4 3-9 5-5 5-26 15-10
INTR# pin 5-2 5-8
Invalid opcode exception (#UD) 2-15 5-28 5-29 5-53 11-1 13-3 15-4 18-5 18-12 18-24 18-26
Invalid TSS exception (#TS) 5-35 5-36 6-8
Invalid-operation exception, x87 FPU 18-13 18-16
INVD instruction 2-21 4-26 7-14 10-18 18-4
INVLPG instruction 2-21 4-26 7-14 18-4
IOPL (I/O privilege level) field, EFLAGS register, description of 2-8
IOPL (I/O privilege level) field, EFLAGS register, restoring on return from exception or interrupt handler 5-16
IOPL (I/O privilege level) field, EFLAGS register, sensitive instructions in virtual-8086 mode 16-14
IOPL (I/O privilege level) field, EFLAGS register, virtual interrupt 2-9 2-10
IPI see "Interprocessor interrupt"
IRET instruction 3-9 5-8 5-9 5-16 5-17 6-12 6-13 7-14 16-6 16-27
IRETD instruction 2-9 7-14
IRR (interrupt request register), local APIC 8-36
JMP instruction 2-4 3-9 4-12 4-13 4-18 6-3 6-12 6-13
KEN# pin 10-14 18-40
L0-L3 (local breakpoint enable) flags, DR7 register 15-5
L1 (level 1) cache, caching methods 10-5
L1 (level 1) cache, description of 10-3
L1 (level 1) cache, effect of using write-through memory 10-8
L1 (level 1) cache, introduction of 18-31
L1 (level 1) cache, invalidating and flushing 10-18
L1 (level 1) cache, MESI cache protocol 10-9
L2 (level 2) cache, caching methods 10-5
L2 (level 2) cache, description of 10-3
L2 (level 2) cache, disabling 10-19
L2 (level 2) cache, effect of using write-through memory 10-8
L2 (level 2) cache, introduction of 18-31
L2 (level 2) cache, invalidating and flushing 10-18
L2 (level 2) cache, MESI cache protocol 10-9
L3 (level 3) cache, caching methods 10-5
L3 (level 3) cache, description of 10-3
L3 (level 3) cache, disabling and enabling 10-14 10-18
L3 (level 3) cache, effect of using write-through memory 10-8
L3 (level 3) cache, introduction of 18-33
L3 (level 3) cache, invalidating and flushing 10-18
L3 (level 3) cache, MESI cache protocol 10-9
LAR instruction 2-21 4-27
Larger page sizes, introduction of 18-33
Larger page sizes, support for 18-23
Last branch, interrupt, and exception recording, description of 15-11 15-13 15-14 15-19
LastBranchFromIP MSR 15-21
LastBranchToIP MSR 15-21
LastExceptionFromIP MSR 15-16 15-21
LastExceptionTolP MSR 15-16 15-21
LBR (last branch/interrupt/exception) flag, DebugCtlMSR MSR 15-12 15-15 15-20 15-21
LDS instruction 3-9 4-10
LDT, associated with a task 6-3
LDT, description of 2-3 2-4 3-17
LDT, index into with index field of segment selector 3-7
LDT, pointer to in TSS 6-6
LDT, pointers to exception and interrupt handlers 5-14
LDT, segment descriptors in 3-9
LDT, segment selector field, TSS 6-18
LDT, selecting with TI (table indicator) flag of segment selector 3-7
LDT, setting up during initialization 9-12
LDT, task switching 6-12
LDT, task-gate descriptor 6-9
LDT, use in address translation 3-7
LDTR register, description of 2-3 2-4 2-5 2-11 3-17
LDTR register, limit 4-5
LDTR register, storing 3-17
LE (local exact breakpoint enable) flag, DR7 register 15-5 15-9
LEN0-LEN3 (Length) fields, DR7 register 15-6
LES instruction 3-9 4-10 5-28
LFENCE instruction 2-14 7-8 7-11 7-12 7-14
LFS instruction 3-9 4-10
LGDT instruction 2-20 4-26 7-14 9-12 18-24
LGS instruction 3-9 4-10
LIDT, instruction 2-20 4-26 5-12 7-14 9-10 16-6 18-27
Limit checking, description of 4-5
Limit checking, pointer offsets are within limits 4-29
Limit field, segment descriptor 4-2 4-5
Linear address space 3-6
Linear address space of task 6-19
Linear address space, defined 3-1
Linear address, description of 3-6
Linear address, introduction to 2-5
Link (to previous task) field, TSS 5-18
Linking tasks, mechanism 6-16
Linking tasks, modifying task linkages 6-18
LINT pins, function of 5-2
LINT pins, programming D-1
LLDT instruction 2-20 4-26 7-14
LMSW instruction 2-20 4-26
Local APIC, APIC_BASE_MSR 8-11
Local APIC, arbitration over the APIC bus 8-31
Local APIC, arbitration over the system bus 8-31
Local APIC, block diagram 8-6
Local APIC, cluster model 8-29
Local APIC, current-count register 8-20
Local APIC, description of 8-1
Local APIC, detecting with CPUID instruction 8-9
Local APIC, DFR (destination format register) 8-28
Local APIC, differences between local APIC and 82489DX 18-28
Local APIC, disabling 8-10
Local APIC, divide configuration register 8-20
Local APIC, enabling 8-10
Local APIC, external interrupts 5-2
Local APIC, focus processor 8-30
Local APIC, IA32_APIC_BASE MSR 8-11
Local APIC, indicating performance-monitoring counter overflow 15-62
Local APIC, initial-count register 8-20
Local APIC, internal error interrupts 8-2
Local APIC, interrupt command register (ICR) 8-21
Local APIC, interrupt destination 8-31
Local APIC, interrupt distribution mechanism 8-29
Local APIC, interrupt sources 8-2
Local APIC, IRR (interrupt request register) 8-36
Local APIC, local vector table (LVT) 8-15
Local APIC, logical destination mode 8-28
Local APIC, LVT (local-APIC version register) 8-14
Local APIC, MDA (message destination address) 8-28
Local APIC, new features incorporated in the Pentium 4 and Intel Xeon processors 18-29
Local APIC, new features incorporated in the Pentium and P6 family processors 18-28
Local APIC, overview of 8-1
Local APIC, physical destination mode 8-27
Local APIC, receiving external interrupts 5-2
Local APIC, register address map 8-8
Local APIC, relationship of local APIC to I/O APIC 8-3 8-4
Local APIC, SMI interrupt 13-2
Local APIC, spurious interrupt 8-38
Local APIC, state after a software (INIT) reset 8-13
Local APIC, state after INIT-deassert message 8-14
Local APIC, state after power-up reset 8-12
Local APIC, state of 8-39
Local APIC, SVR (spurious-interrupt vector register) 8-10
Local APIC, timer 8-20
Local APIC, timer generated interrupts 8-2
Local APIC, TMR (trigger mode register) 8-36
Local APIC, valid interrupts 8-18
Local APIC, version register 8-14
Local Descriptor Table see "LDT"
Local descriptor table register see "LDTR"
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