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| Intel Corporation — IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide |
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| Предметный указатель |
Data segments, description of 3-13
Data segments, descriptor layout 4-3
Data segments, expand-down type 3-12
Data segments, paging of 2-5
Data segments, privilege level checking when accessing 4-10
DE (debugging extensions) flag, CR4 control register 2-17 18-21 18-23 18-24
Debug exception (#DB) 5-9 5-23 6-6 15-1 15-7 15-15 15-21
Debug registers, description of 15-2
Debug registers, introduction to 2-5
Debug registers, loading 2-21
Debug store see "DS"
DebugCtlMSR MSR 15-11 15-19 15-21
Debugging facilities see "DS (debug store) mechanism"
Debugging facilities, debug registers 15-2
Debugging facilities, exceptions 15-6
Debugging facilities, last branch, interrupt, and exception recording 15-11 15-19
Debugging facilities, masking debug exceptions 5-9
Debugging facilities, overview of 15-1
Debugging facilities, performance-monitoring counters 15-23
DEC instruction 7-5
Denormal operand exception (#D) 18-11
Denormalized operand 18-14
Device-not-available exception (#NM) 2-14 2-20 5-30 5-31 9-8 18-12 18-13
DIV instruction 5-22
Divide configuration register, local APIC 8-20
Divide-error exception (#DE) 5-22 18-25
Double-fault exception (#DF) 5-32 5-33 18-27
DPL (descriptor privilege level) field, segment descriptor 3-11 4-2 4-9
DR0-DR3 breakpoint-address registers 15-1 15-3 15-15 15-20 15-21
DR4-DR5 debug registers 15-4 18-24
DR6 debug status register 15-1 15-4
DR6 debug status register, B0-B3 (breakpoint condition detected) flags 15-4
DR6 debug status register, BD (debug register access detected) flag 15-4
DR6 debug status register, BS (single step) flag 15-4
DR6 debug status register, BT (task switch) flag 15-4
DR6 debug status register, debug exception (#DB) 5-23
DR6 debug status register, reserved bits 18-24
DR7 debug control register 15-1 15-4
DR7 debug control register, G0-G3 (global breakpoint enable) flags 15-5
DR7 debug control register, GD (general detect enable) flag 15-5
DR7 debug control register, GE (global exact breakpoint enable) flag 15-5
DR7 debug control register, L0-L3 (local breakpoint enable) flags 15-5
DR7 debug control register, LE local exact breakpoint enable) flag 15-5
DR7 debug control register, LEN0-LEN3 (Length) fields 15-6
DR7 debug control register, R/W0-R/W3 (read/write) fields 15-5 18-24
DS (debug store) mechanism, availability of 15-33
DS (debug store) mechanism, description of 15-33
DS (debug store) mechanism, DS feature flag, CPUID instruction 15-33
DS (debug store) mechanism, DS save area 15-33
DS (debug store) mechanism, interrupt service routine (DS ISR) 15-18
DS (debug store) mechanism, setting up 15-17
DS feature flag, CPUID instruction 15-11
DS save area 15-35
E (edge detect) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-59
E (expansion direction) flag, segment descriptor 4-2 4-5
E (MTRRs enabled) flag, IA32_MTRR_DEF_TYPE MSR 10-26
EFLAGS register, introduction to 2-5
EFLAGS register, new flags 18-5
EFLAGS register, saved in TSS 6-6
EFLAGS register, saving on call to exception or interrupt handler 5-15
EFLAGS register, system flags 2-7
EFLAGS register, using flags to distinguish between 32-bit IA-32 processors 18-6
EIP register 18-12
EIP register, saved in TSS 6-6
EIP register, saving on call to exception or interrupt handler 5-15
EIP register, state following initialization 9-6
EM (emulation) flag, CR0 control register 2-14 2-15 5-30 9-6 9-7 11-1 12-3
EMMS instruction 11-3
Error code, exception, description of 5-18
Error code, pushing on stack 18-35
Error signals 18-12
ERROR# input 18-19
ERROR# output 18-19
ES0 and ES1 (event select) fields, CESR MSR (Pentium processor) 15-63
ESP register, saving on call to exception or interrupt handler 5-15
ET (extension type) flag, CR0 control register 2-14 18-8
Event select field, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-58
Events, at-retirement 15-44
Events, at-retirement (Pentium 4 processor) 15-26 A-25
Events, non-retirement (Pentium 4 processor) 15-26 A-1
Events, P6 family processors A-38
Events, Pentium processor A-49
Exception handler, calling 5-14
Exception handler, defined 5-1
Exception handler, flag usage by handler procedure 5-17
Exception handler, machine-check exceptions (#MC) 14-15
Exception handler, procedures 5-14
Exception handler, protection of handler procedures 5-16
Exception handler, task 5-18 6-3
Exceptions, alignment check 18-13
Exceptions, classifications 5-6
Exceptions, conditions checked during a task switch 6-15
Exceptions, coprocessor segment overrun 18-13
Exceptions, description of 2-4 5-1
Exceptions, device not available 18-13
Exceptions, double fault 5-32 5-33
Exceptions, error code 5-18
Exceptions, floating-point error 18-14
Exceptions, general protection 18-14
Exceptions, handler mechanism 5-14
Exceptions, handler procedures 5-14
Exceptions, handling 5-14
Exceptions, handling in real-address mode 16-6
Exceptions, handling in SMM 13-10
Exceptions, handling in virtual-8086 mode 16-15
Exceptions, handling through a task gate in virtual-8086 mode 16-20
Exceptions, handling through a trap or interrupt gate in virtual-8086 mode 16-17
Exceptions, IDT 5-11
Exceptions, initializing for protected-mode operation 9-12
Exceptions, invalid-opcode 18-5
Exceptions, masking debug exceptions 5-9
Exceptions, masking when switching stack segments 5-10
Exceptions, MMX instructions 11-1
Exceptions, notation 1-9
Exceptions, overview of 5-1
Exceptions, priorities among simultaneous exceptions and interrupts 5-10
Exceptions, priority of 18-26
Exceptions, priority of, x87 FPU exceptions 18-12
Exceptions, reference information on all exceptions 5-20
Exceptions, restarting a task or program 5-6
Exceptions, segment not present 18-13
Exceptions, sources of 5-5
Exceptions, summary of 5-3
Exceptions, vectors 5-2
Execution events A-31
Expand-down data segment type 3-12
External bus errors, detected with machine-check architecture 14-14
F2XM1 instruction 18-16
Fast string operations 7-10
Faults, description of 5-6
Faults, restarting a program or task after 5-7
FCMOVcc instructions 18-4
FCOMI instruction 18-4
FCOMIP instruction 18-4
FCOS instruction 18-15
FDISI instruction (obsolete) 18-18
FDIV instruction 18-13 18-14
FE (fixed MTRRs enabled) flag, IA32_MTRR_DEF_TYPE MSR 10-26
Feature, determination, of processor 18-2
Feature, information, processor 18-2
FENI instruction (obsolete) 18-18
FINIT/FNINIT instructions 18-8 18-19
FIX (fixed range registers supported) flag, A32_MTRRCAPMSR 10-25
Fixed-range MTRRs, description of 10-26
Fixed-range MTRRs, mapping to physical memory 10-27
Flat segmentation model 3-3
FLD instruction 18-16
FLDENV instruction 18-13 18-14
FLDL2E instruction 18-16
FLDL2T instruction 18-17
| FLDLG2 instruction 18-16
FLDLN2 instruction 18-16
FLDPI instruction 18-16
Floating-point error exception (#MF) 18-14
Floating-point exceptions, denormal operand exception (#D) 18-11
Floating-point exceptions, invalid operation (#I) 18-16
Floating-point exceptions, numeric overflow (#O) 18-11
Floating-point exceptions, numeric underflow (#U) 18-11
Floating-point exceptions, saved CS and EIP values 18-12
FLUSH# pin 5-4
FNSAVE instruction 11-4
Focus processor, local APIC 8-30
FPATAN instruction 18-16
FPREM instruction 18-8 18-13 18-14 18-15
FPREM1 instruction 18-8 18-15
FPTAN instruction 18-9 18-15
Front_end events A-30
FRSTOR instruction 11-4 18-13 18-14
FSAVE instruction 11-3 11-4
FSAVE/FNSAVE instructions 18-13 18-17
FSCALE instruction 18-14
FSIN instruction 18-15
FSINCOS instruction 18-15
FSQRT instruction 18-13 18-14
FSTENV instruction 11-3
FSTENV/FNSTENV instructions 18-17
FTAN instruction 18-9
FUCOM instruction 18-15
FUCOMI instruction 18-4
FUCOMIP instruction 18-4
FUCOMP instruction 18-15
FUCOMPP instruction 18-15
FWAIT instruction 5-30
FXAM instruction 18-16 18-17
FXRSTOR instruction 2-17 9-9 11-3 11-4 11-5 12-1 12-2 12-6
FXSAVE instruction 2-17 9-9 11-3 11-4 11-5 12-1 12-2 12-6
FXSR feature flag, CPUID instruction 9-9
FXTRACT instruction 18-11 18-16
G (global) flag, page-directory entries 10-13 10-21
G (global) flag, page-table entries 3-27 10-13 10-21
G (granularity) flag, segment descriptor 3-10 3-12 4-2 4-5
G0-G3 (global breakpoint enable) flags, DR7 register 15-5
Gate descriptors, call gates 4-17
Gate descriptors, description of 4-16
Gates 2-3
GD (general detect enable) flag, DR7 register 15-5 15-9
GDT, description of 2-3 3-16
GDT, index into with index field of segment selector 3-7
GDT, initializing 9-12
GDT, paging of 2-5
GDT, pointers to exception and interrupt handlers 5-14
GDT, segment descriptors in 3-9
GDT, selecting with TI (table indicator) flag of segment selector 3-7
GDT, task switching 6-12
GDT, task-gate descriptor 6-9
GDT, TSS descriptors 6-7
GDT, use in address translation 3-7
GDTR register, description of 2-3 2-5 2-10 3-16
GDTR register, limit 4-5
GDTR register, loading during initialization 9-12
GDTR register, storing 3-17
GE (global exact breakpoint enable) flag, DR7 register 15-5 15-9
General-detect exception condition 15-9
General-protection exception (#GP) 3-13 4-7 4-8 4-14 4-15 5-12 5-17 5-41 5-42 5-43 6-7 15-2 18-14 18-25 18-26 18-36 18-38
General-purpose registers, saved in TSS 6-5
Global Descriptor Table see "GDT"
Global descriptor table register see "GDTR"
HALT state, relationship to SMI interrupt 13-4 13-14
Hardware reset, description of 9-1
Hardware reset, processor state after reset 9-2
Hardware reset, state of MTRRs following 10-23
Hardware reset, value of SMBASE following 13-4
hexadecimal numbers 1-8
HITM# line 10-5
HLT instruction 2-22 4-26 5-33 13-14 13-15 15-22
Hyper-Threading technology, architectural state of a logical processor 7-24
Hyper-Threading technology, architecture description 7-24
Hyper-Threading technology, caches 7-29
Hyper-Threading technology, debug registers 7-27
Hyper-Threading technology, description of 7-23 18-3
Hyper-Threading technology, detecting 7-31
Hyper-Threading technology, executing multiple threads 7-32
Hyper-Threading technology, execution-based timing loops 7-41
Hyper-Threading technology, external signal compatibility 7-30
Hyper-Threading technology, halting logical processors 7-41
Hyper-Threading technology, handling interrupts 7-33
Hyper-Threading technology, HLT instruction 7-34
Hyper-Threading technology, IA32_MISC_ENABLE MSR 7-28
Hyper-Threading technology, implementation of in IA-32 processors 7-23
Hyper-Threading technology, implementation specific features 7-29
Hyper-Threading technology, initializing IA-32 processors with 7-32
Hyper-Threading technology, introduction of into the IA-32 architecture 18-3
Hyper-Threading technology, local APIC, functionality in logical processor 7-26
Hyper-Threading technology, logical processors, identifying 7-34
Hyper-Threading technology, machine check architecture 7-27
Hyper-Threading technology, managing idle and blocked conditions 7-34
Hyper-Threading technology, memory ordering 7-28
Hyper-Threading technology, microcode update resources 7-28
Hyper-Threading technology, MP systems 7-33
Hyper-Threading technology, MTRRs 7-26
Hyper-Threading technology, PAT 7-27
Hyper-Threading technology, PAUSE instruction 7-34
Hyper-Threading technology, performance monitoring 15-51
Hyper-Threading technology, performance monitoring counters 7-28
Hyper-Threading technology, proper placement of locks and semaphores 7-42
Hyper-Threading technology, required operating system support 7-40
Hyper-Threading technology, scheduling multiple threads 7-41
Hyper-Threading technology, self modifying code 7-29
Hyper-Threading technology, serializing instructions 7-28
Hyper-Threading technology, spin-wait loops, using PAUSE instructions in 7-40
Hyper-Threading technology, thermal monitor 7-30
Hyper-Threading technology, TLBs 7-30
I/O APIC 8-31
I/O APIC, additional information about 8-1
I/O APIC, bus arbitration 8-31
I/O APIC, description of 8-1
I/O APIC, external interrupts 5-4
I/O APIC, interrupt sources 8-2
I/O APIC, overview of 8-1
I/O APIC, relationship of local APIC to I/O APIC 8-3 8-4
I/O APIC, valid interrupts 8-18
I/O privilege level see "IOPL"
I/O, breakpoint exception conditions 15-9
I/O, I/O permission bit map, TSS 6-6
I/O, in virtual-8086 mode 16-14
I/O, instruction restart flag, SMM revision indentifier field 13-16
I/O, instructions, restarting following an SMI interrupt 13-16
I/O, map base address field, TSS 6-6
IA-32 Intel architecture, compatibility 18-1
IA-32 Intel architecture, processors 18-1
IA32_APIC_BASE MSR 7-16 7-17 8-9 8-10 8-11 B-2
IA32_BIOS_SIGN_ID MSR B-4
IA32_BIOS_UPDT_TRIG MSR 9-35 B-4
IA32_CTL MSR B-5
IA32_DEBUGCTL MSR 15-11 15-12 15-15 15-16 15-18 15-19 15-33 B-9
IA32_DS_AREA MSR 15-16 15-17 15-24 15-34 15-48 B-15
IA32_MCG_CAP MSR 14-2 14-15 B-5
IA32_MCG_CTL MSR 14-2 14-5
IA32_MCG_EAX MSR 14-8 B-5
IA32_MCG_EBP MSR 14-9 B-6
IA32_MCG_EBX MSR 14-8 B-5
IA32_MCG_ECX MSR 14-8 B-5
IA32_MCG_EDI MSR 14-9 B-5
IA32_MCG_EDX MSR 14-8 B-5
IA32_MCG_EFLAGS MSR 14-9 B-6
IA32_MCG_EIP MSR 14-9 B-6
IA32_MCG_ESI MSR 14-8 B-5
IA32_MCG_ESP MSR 14-9 B-6
IA32_MCG_MISC MSR 14-5 B-7
IA32_MCG_STATUS MSR 14-2 14-4 14-16 14-18
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