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| Intel Corporation — IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide |
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| Предметный указатель |
Paging, 36-bit physical addressing, using PSE-36, paging mechanism 3-34
Paging, combining segment and page-level protection 4-34
Paging, combining with segmentation 3-6
Paging, defined 3-1
Paging, initializing 9-12
Paging, introduction to 2-5
Paging, large page size MTRR considerations 10-37
Paging, mapping segments to pages 3-36
Paging, mixing 4-KByte and 4-MByte pages 3-22
Paging, options 3-18
Paging, overview 3-17
Paging, page 3-19
Paging, page boundaries regarding TSS 6-6
Paging, page directory 3-19
Paging, page sizes 3-20
Paging, page table 3-19
Paging, page-directory-pointer table 3-19
Paging, page-fault exception 5-44 5-45 5-46
Paging, page-level protection 4-2 4-31
Paging, page-level protection flags 4-32
Paging, physical address sizes 3-20
Paging, virtual-8086 tasks 16-10
Parameter passing, between 16- and 32-bit call gates 17-7
Parameter translation, between 16- and 32-bit code segments 17-8
Pause instruction 2-14
PBi (performance monitoring /breakpoint pins) flags, DebugCtlMSR MSR 15-20
PC (pin control) flag, PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-59
PC0 and PC1 (pin control) fields, CESR MSR (Pentium processor) 15-64
PCD (page-level cache disable) flag, CR3 control register 2-16 10-13 18-22 18-32
PCD (page-level cache disable) flag, page-directory entries 9-8 10-13 10-14 10-37
PCD (page-level cache disable) flag, page-table entries 3-26 9-8 10-13 10-14 10-37 18-33
PCD pin (Pentium processor) 10-14
PCE (performance monitoring counter enable) flag, CR4 control register 2-17 4-27 15-30 15-60
PCE (performance-monitoring counter enable) flag, CR4 control register 18-21
PDBR see "CR3 control register"
PE (protection enable) flag, CR0 control register 2-16 4-2 9-13 9-14 13-9
PEBS (precise event-based sampling) facilities, availability of 15-48
PEBS (precise event-based sampling) facilities, description of 15-27 15-47
PEBS (precise event-based sampling) facilities, DS save area 15-33
PEBS (precise event-based sampling) facilities, PEBS buffer 15-34 15-48
PEBS (precise event-based sampling) facilities, PEBS records 15-33 15-36
PEBS (precise event-based sampling) facilities, PEBS_UNAVAILABLE flag, IA32_MISC_ENABLE MSR B-8
PEBS (precise event-based sampling) facilities, writnga PEBS interrupt service routine 15-18 15-49
PEBS_UNAVAILABLE flag, IA32_MISC_ENABLE MSR 15-34 B-8
Pentium 4 processor 1-1
Pentium 4 processor, compatibility with floating-point software 18-7
Pentium 4 processor, list of performance-monitoring events A-1
Pentium 4 processor, MSRs supported B-1
Pentium II processor 1-1
Pentium III processor 1-1
Pentium Pro processor 1-1
Pentium processor 1-1
Pentium processor, list of performance-monitoring events A-49
Pentium processor, MSR supported by B-25
Pentium processor, performance-monitoring counters 15-62
Pentium processors 18-7
PerfCtr0 and PerfCtrl MSRs (P6 family processors) 15-58 15-60
PerfEvtSel0 and PerfEvtSel1 MSRs (P6 family processors) 15-58
Performance events, at-retirement events (Pentium 4 processor) A-25
Performance events, non-retirement events (Pentium 4 processor) A-1
Performance events, P6 family processors A-38
Performance events, Pentium processor A-49
Performance-monitoring counters, description of 15-23
Performance-monitoring counters, events that can be counted (P6 family processors) A-38
Performance-monitoring counters, events that can be counted (Pentium 4 processor) A-1
Performance-monitoring counters, events that can be counted (Pentium processors) 15-65 A-49
Performance-monitoring counters, interrupt 8-2
Performance-monitoring counters, introduction of in IA-32 processors 18-41
Performance-monitoring counters, monitoring counter overflow (P6 family processors) 15-62
Performance-monitoring counters, overflow, monitoring (P6 family processors) 15-62
Performance-monitoring counters, overview of 2-6
Performance-monitoring counters, P6 family processors 15-57
Performance-monitoring counters, Pentium II processor 15-57
Performance-monitoring counters, Pentium Pro processor 15-57
Performance-monitoring counters, Pentium processor 15-62
Performance-monitoring counters, reading 2-22 15-60
Performance-monitoring counters, setting up (P6 family processors) 15-58
Performance-monitoring counters, software drivers for 15-61
Performance-monitoring counters, starting and stopping 15-61
PG (paging) flag, CR0 control register 2-13 3-18 3-26 3-28 3-34 4-2 9-13 9-14 13-9 18-33
PGE (page global enable) flag, CR4 control register 2-17 3-27 10-13 18-21 18-22
PhysBase field, IA32_MTRR_PHYSBASEn MTRR 10-28
Physical address extension, accessing full extended physical address space 3-31
Physical address extension, introduction to 3-6
Physical address extension, page-directory entries 3-31 3-35
Physical address extension, page-table entries 3-31
Physical address extension, using PAE paging mechanism 3-28
Physical address extension, using PSE-32 paging mechanism 3-34
Physical address space, 4 GBytes 3-6
Physical address space, 64 Gbytes 3-6
Physical address space, defined 3-1
Physical address space, description of 3-6
Physical address space, mapped to a task 6-19
Physical addressing 2-5
Physical destination mode, local APIC 8-27
Physical memory, mapping of with fixed-range MTRRs 10-27
Physical memory, mapping of with variable-range MTRRs 10-27
PhysMask, IA32_MTRR_PHYSMASKn MTRR 10-28
PM0/BP0 and PM1/BP1 (performance-monitor) pins (Pentium processor) 15-62 15-64 15-65
Pointers, code-segment pointer size 17-5
Pointers, limit checking 4-29
Pointers, validation 4-27
POP instruction 3-9
POPF instruction 5-9 15-10
Precise event-based sampling see "PEBS"
PREFETCHh instruction 2-14 10-4 10-19
Previous task link field, TSS 6-6 6-16 6-18
Priority levels, APIC interrupts 8-34
Privilege levels, checking when accessing data segments 4-10
Privilege levels, checking, for call gates 4-18
Privilege levels, checking, when transferring program control between code segments 4-12
Privilege levels, description of 4-7
Privilege levels, protection rings 4-9
Privileged instructions 4-26
Processor management, initialization 9-1
Processor management, local APIC 8-1
Processor management, overview of 7-1
Processor management, snooping mechanism 7-9
Processor ordering, description of 7-7
Protected mode, IDT initialization 9-12
Protected mode, initialization for 9-11
Protected mode, mixing 16-bit and 32-bit code modules 17-2
Protected mode, mode switching 9-13
Protected mode, PE flag, CR0 register 4-2
Protected mode, switching to 4-2 9-14
Protected mode, system data structures required during initialization 9-11 9-12
Protection rings 4-9
Protection, combining segment and page-level protection 4-34
Protection, disabling 4-2
Protection, enabling 4-2
Protection, flags used for page-level protection 4-2
Protection, flags used for segment-level protection 4-2
Protection, of exception- and interrupt-handler procedures 5-16
Protection, overview of 4-1
Protection, page level 4-2 4-31 4-33
Protection, page level, overriding 4-33
Protection, page-level protection flags 4-32
Protection, read/write, page level 4-33
Protection, segment level 4-2
Protection, user/supervisor type 4-32
PS (page size) flag, page-table entries 3-27
PSE (page size extension) flag, CR4 control register 2-17 3-18 3-21 3-22 3-34 10-21 18-21 18-23
PSE-36 feature flag, CPUID instruction 3-19 3-34
PSE-36 page size extension 3-6
Pseudo-infinity 18-10
Pseudo-NaN 18-10
Pseudo-zero 18-10
PUSH instruction 18-6
PUSHF instruction 5-9 18-7
PVI (protected-mode virtual interrupts) flag, CR4 control register 2-9 2-10 2-16 18-21
| PWT (page-level write-through) flag, CR3 control register 2-16 10-13 18-22 18-32
PWT (page-level write-through) flag, page-directory entries 9-8 10-13 10-37
PWT (page-level write-through) flag, page-table entries 3-26 9-8 10-13 10-37 18-33
PWT pin (Pentium processor) 10-14
QNaN, compatibility, IA-32 processors 18-10
R/S# pin 5-4
R/W (read/write) flag, page-directory entry 4-2 4-3 4-33
R/W (read/write) flag, page-table entries 3-25
R/W (read/write) flag, page-table entry 4-2 4-3 4-33
R/W0-R/W3 (read/write) fields, DR7 register 15-5 18-24
RDMSR instruction 2-23 4-26 15-14 15-21 15-23 15-30 15-58 15-60 15-62 18-4 18-39
RDPMC instruction 2-22 4-26 15-30 15-58 15-60 18-4 18-21 18-41
RDTSC instruction 2-22 4-26 15-22 18-4
Read/write protection, page level 4-33
Read/write rights, checking 4-28
Real-address mode, 8086 emulation 16-1
Real-address mode, address translation in 16-3
Real-address mode, description of 16-1
Real-address mode, exceptions and interrupts 16-8
Real-address mode, IDT initialization 9-10
Real-address mode, IDT, changing base and limit of 16-6
Real-address mode, IDT, structure of 16-7
Real-address mode, IDT, use of 16-6
Real-address mode, initialization 9-10
Real-address mode, instructions supported 16-4
Real-address mode, interrupt and exception handling 16-6
Real-address mode, interrupts 16-8
Real-address mode, introduction to 2-6
Real-address mode, mode switching 9-13
Real-address mode, native 16-bit mode 17-1
Real-address mode, overview of 16-1
Real-address mode, registers supported 16-4
Real-address mode, switching to 9-15
Related literature 1-9
Replay events A-32
Requested privilege level see "RPL"
reserved bits 1-6 18-1
RESET# pin 5-4 18-19
RESET# signal 2-22
Restarting program or task, following an exception or interrupt 5-6
Restricting addressable domain 4-32
RET instruction 4-12 4-13 4-24 17-7
Returning from a called procedure 4-24
Returning from an interrupt or exception handler 5-16
RF (resume) flag, EFLAGS register 2-9 5-9 15-1
RPL, description of 3-8 4-9
RPL, field, segment selector 4-2
RSM instruction 2-22 7-14 13-1 13-2 13-3 13-12 13-16 18-5
S (descriptor type) flag, segment descriptor 3-11 3-13 4-2 4-6
SBB instruction 7-5
Segment descriptors, access rights 4-27
Segment descriptors, access rights, invalid values 18-23
Segment descriptors, automatic bus locking while updating 7-4
Segment descriptors, base address fields 3-11
Segment descriptors, code type 4-3
Segment descriptors, D/B (default operation size/default stack pointer size and/or upper bound) flag 3-11 4-5
Segment descriptors, data type 4-3
Segment descriptors, description of 2-3 3-9
Segment descriptors, DPL (descriptor privilege level) field 3-11 4-2
Segment descriptors, E (expansion direction) flag 4-2 4-5
Segment descriptors, G (granularity) flag 3-12 4-2 4-5
Segment descriptors, limit field 4-2 4-5
Segment descriptors, loading 18-23
Segment descriptors, P (segment-present) flag 3-11
Segment descriptors, S (descriptor type) flag 3-11 3-13 4-2 4-6
Segment descriptors, segment limit field 3-10
Segment descriptors, system type 4-3
Segment descriptors, tables 3-15
Segment descriptors, TSS descriptor 6-7
Segment descriptors, type field 3-11 3-13 4-2 4-6
Segment descriptors, type field, encoding 3-13 3-15
Segment descriptors, when P (segment-present) flag is clear 3-12
Segment limit, checking 2-21
Segment limit, field, segment descriptor 3-10
Segment not present exception (#NP) 3-11
Segment registers, description of 3-8
Segment registers, saved in TSS 6-6
Segment selectors, description of 3-7
Segment selectors, index field 3-7
Segment selectors, null 4-7
Segment selectors, RPL field 3-8 4-2
Segment selectors, TI (table indicator) flag 3-7
Segment-not-present exception (#NP) 5-37 5-38
Segmented addressing 1-8
Segments, basic flat model 3-3
Segments, code type 3-13
Segments, combining segment and page-level protection 4-34
Segments, combining with paging 3-6
Segments, data type 3-13
Segments, defined 3-1
Segments, disabling protection of 4-2
Segments, enabling protection of 4-2
Segments, mapping to pages 3-36
Segments, multisegment usage model 3-5
Segments, protected flat model 3-3
Segments, segment-level protection 4-2
Segments, segment-not-present exception 5-37 5-38
Segments, system 2-3
Segments, types, checking access rights 4-27
Segments, typing 4-6
Segments, using 3-3
Segments, wraparound 18-36
Self-modifying code, effect on caches 10-19
Serializing instructions 7-14 18-18
SF (stack fault) flag, x87 FPU status word 18-9
SFENCE instruction 2-14 7-8 7-11 7-12 7-14
SGDT instruction 2-20 3-17
Shutdown, resulting from double fault 5-33
Shutdown, resulting from out of IDT limit condition 5-33
SIDT instruction 2-20 3-17 5-12
SIMD floating-point exception (#XF) 2-18 5-53 5-54 5-55 9-9
SIMD floating-point exceptions, description of 5-53 12-5
SIMD floating-point exceptions, handler 12-2
SIMD floating-point exceptions, support for 2-18
Single-stepping breakpoint exception condition 15-10
Single-stepping on branches 15-15
Single-stepping on exceptions 15-15
Single-stepping on interrupts 15-15
Single-stepping TF (trap) flag, EFLAGS register 15-10
SLDT instruction 2-20
SLTR instruction 3-17
SMBASE, default value 13-4
SMBASE, relocation of 13-15
SMI handler, description of 13-1
SMI handler, execution environment for 13-9
SMI handler, exiting from 13-3
SMI handler, location in SMRAM 13-4
SMI interrupt 2-22 8-5
SMI interrupt, description of 13-1 13-2
SMI interrupt, priority 13-3
SMI interrupt, switching to SMM 13-2
SMI# pin 5-4 13-2 13-16
SMM, auto halt restart 13-14
SMM, executing the HLT instruction in 13-15
SMM, exiting from 13-3
SMM, handling exceptions and interrupts 13-10
SMM, I/O instruction restart 13-16
SMM, introduction to 2-6
SMM, native 16-bit mode 17-1
SMM, overview of 13-1
SMM, revision identifier 13-13
SMM, revision identifier field 13-13
SMM, switching to 13-3
SMM, switching to from other operating modes 13-2
SMM, using x87 FPU in 13-12
SMRAM, caching 13-8
SMRAM, description of 13-1
SMRAM, state save map 13-5
SMRAM, structure of 13-4
SMSW instruction 2-20
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