Уэйкерли Дж.Ф. — Проектирование цифровых устройств (том 1) :: Электронная библиотека попечительского совета мехмата МГУ

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Уэйкерли Дж.Ф. — Проектирование цифровых устройств (том 1)

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Название: Проектирование цифровых устройств (том 1)

Автор: Уэйкерли Дж.Ф.

Аннотация:

Основополагающий учебник, в котором рассмотрены все направления современной цифровой электроники. Особое внимание уделено программируемым логическим интегральным схемам (ПЛИС).
Предназначен для студентов, аспирантов и преподавателей ВУЗов, разработчиков аппаратуры.

Язык:

Статус предметного указателя: Готов указатель с номерами страниц

ed2k: ed2k stats

Год издания: 2002

Количество страниц: 1087

Добавлена в каталог: 31.03.2006

Операции: Положить на полку | Скопировать ссылку для форума | Скопировать ID

Предметный указатель

IC type      386
Identifier      298 321
IEEE Standard Graphic Symbols for Logic Functions      374
If statement      347 734
Implies      273
In-circuit testing      1043
In-system programmability      412
Includes      273
Independent error model      85
Induction step      245
Inequality      497
Infant mortality      1050
Inferred latch      789
Information bit      86
Initial state      661
Input state      706
Input-list      304 312
Inputs      397
Instantiate      336
INTEGER      324
Integrated circuit      32 113
Intermediate equation      301
Internal feedback      802
Internal state      706
Inversion bubble      110 374
Inverted 1-out-of-n code      82
Inverter      28 110
IOB      1012 1021
Irredundant sum      364
istype      300
Iterative circuit      490
J-K application table      674
Johnson counter      842
JTAG port      412
Juxtaposition      241
Karnaugh map      267
Keyword      321
Label      336
Large-scale integration      35
Latch      626
Latch-up      143
Late-write SSRAM with flow-through outputs      992
Late-write SSRAM with pipelined outputs      994
Leakage current      116 181
Least significant bit      51
Least significant digit      50
Left      828
Level shifter      214
Level translator      214
LFSR counter      845
Library      333
Library clause      334
Line code      96
Linear encoding      978
Linear feedback shift-register      845
Literal      252
Logic diagram      370
Logic family      113
Logic value      108
Logical addition      241
Logical multiplication      240
Lookahead carry circuit      513
Loop statement      349
Low-order      50 51
Low-power Schottky TTL      204
Low-power TTL      203
LOW-state fanout      140 197
LOW-state unit load      197
Low-voltage CMOS      210
Low-voltage TTL      210
LSB      51
LSI      35
m-out-of-n code      82
m-product function      282
m-subcube      84
Magnitude comparator      490
Main machine      701
Manchester code      100
Mask      970
Mask charge      970
Mask ROM      970
Mask-programmable ROM      970
Master      632
Master/slave J-K flip-flop      639
Master/slave S-R flip-flop      638
Matched transmission line      1057
Maximum delay      393
Maximum-length sequence generator      845
Maxterm      252
Maxterm i      253
Maxterm list      253
MCM      41
Mealy machine      645
Mean Time Between Failures      887 1052
Mechanical constraints      1040
Medium-scale integration      35
Metal-oxide semiconductor field-effect transistor      113
Metastability resolution time      885
Metastable state      623
Metatheorem      247
Minimal cut set      709
Minimal product      277
Minimal sum      272
Minimize      266
Minimum delay      393
Minimum distance      86
Minimum pulse width      628
Minterm      252
Minterm i      253
Minterm list      253
Minterm number      253
Minuend      58
Module      298
Modulo-m counter      804
Modulus      804
Moebius counter      842
Moore machine      645
Moore’s Law      41
MOS circuits      114
MOS transistor      113
MOSFET      113
Most significant bit      51
Most significant digit      50
ms      26
MSB      51
MSI      35
MTBF      1052
Multichip module      41
Multiple error      85
Multiple-cycle synchronizer      891
Multiple-output prime implicant      282
Multiple-valued logic      357
Multiplexed address inputs      999
Multiplexer      464
Multiplexing      833
Multiplication dot      240
Multiplying out      243
Mutual exclusion      656 686
Mux      464
n-bit binary counter      805
n-channel MOS transistor      115
n-cube      83
Nail      1043
NAND gate      111
NAND-NAND circuit      263
NBUT gate      762
Negated      376
Negative logic      108
Negative-edge-triggered D flip-flop      634
Nested expansion formula      54

Net      1037
Net list      318 1037
Next statement      350
Next-state logic      644
Nibble      53
Nibble mode      1003
NMOS transistor      115
Node      650
Noise margin      29
Non-Return-to-Zero      96
Non-Return-to-Zero Invert-on-1s      98
Noncode word      85
Noncritical race      712
Nonrecurring engineering cost      39
Nonvolatile memory      961 983
NOR gate      111
NOR-NOR circuit      264
Normal term      252
NOT      300
NOT gate      28 110
NOT operation      240
NPN transistor      185
NRE cost      39
NRZ      96
NRZI      98
ns      26
Null statement      332
OAI gate      124
Observability      1043
Octal number system      51
Odd-parity circuit      481
Odd-parity code      86
OFF      186
Off-set      253
ON      187
On-set      253
One-hot assignment      668
One-time programmable ROM      972
One-to-one mapping      413
Ones’ complement      63
Ones’-complement addition      69
Ones’-complement checksum code      95
Ones’-complement subtraction      70
Open-collector output      203
Open-drain bus      164
Open-drain output      160
Operator overloading      330
OR      300
OR gate      28 110
OR operation      241
OR plane      407
OR-AND circuit      264
OR-AND-INVERT      124
Other declarations      300
Others      328 342
OTP ROM      972
Output enable      126
Output equation      650 707
Output logic      644
Output logic macrocell      797
Output polarity      405
Output stage      192
Output timing skew      857
Output-coded state assignment      645 697
Output-disable time      976 988
Output-enable gate      403
Output-enable input      974
Output-enable time      975 988
Output-hold time      976 988
Output-list      304 312
Outputs      397
Overall fanout      140 197
Overdrive      1044
Overflow      66
Overflow rule      67
Override      1044
P-channel MOS transistor      115
P-set      357
Package      334
Packed-BCD representation      75
Pad ring      210
Page-mode read cycle      1003
Page-mode write cycle      1003
PAL device      37 401
PAL16R6      795
PAL16R8      792
PAL20L8      404
PALCE16V8      407
PALCE20V8      407
PALI6L8      401
Parallel data      96
Parallel-in, parallel-out shift register      826
Parallel-in, serial-out shift register      825
Parallel-to-serial conversion      825
Parity bit      86
Parity-check matrix      88
Partial product      71
Partitioner      924
Parts list      1037
Parts qualification      1036
Passive pull-up      160
PCB      40
PCB traces      40
PECL      222
Permanent failure      84
Phase splitter      192
Physical model      1039
Pin declaration      300
Pin diagram      34
Pin list      1037
Pin locking      1016
Pin number      388 1036
Pinout      34
Pipelined output      646
PLA      37 397
Place and route      318
PLD      37
PLD programmer      411
PMOS transistor      115
pnp transistor      186
Port      322
Port declaration      322
Port map      337
Positional number system      49
Positive ECL      222
Positive logic      108
Positive-edge-triggered D flip-flop      632
Positive-logic convention      239
Postponed-output indicator      639
Postulate      239
Power-dissipation capacitance      153
Power-down input      974
Power-supply rail      131
PR      634
Precedence      241
Precharge voltage      998
Predefined types      324
Preset      626 634
Primary inputs and outputs      490
Prime      240
Prime implicant      273
Prime-implicant table      289
Primitive flow table      720
Principle of superposition      1057
Printed-circuit board      40
Printed-wiring board      40
Priority      442
Priority encoder      441
Procedure      333
Process      344

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