Уэйкерли Дж.Ф. — Проектирование цифровых устройств (том 1) :: Электронная библиотека попечительского совета мехмата МГУ

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Уэйкерли Дж.Ф. — Проектирование цифровых устройств (том 1)

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Название: Проектирование цифровых устройств (том 1)

Автор: Уэйкерли Дж.Ф.

Аннотация:

Основополагающий учебник, в котором рассмотрены все направления современной цифровой электроники. Особое внимание уделено программируемым логическим интегральным схемам (ПЛИС).
Предназначен для студентов, аспирантов и преподавателей ВУЗов, разработчиков аппаратуры.

Язык:

Статус предметного указателя: Готов указатель с номерами страниц

ed2k: ed2k stats

Год издания: 2002

Количество страниц: 1087

Добавлена в каталог: 31.03.2006

Операции: Положить на полку | Скопировать ссылку для форума | Скопировать ID

Предметный указатель

Comparator      490
Comparing numbers      58
Complement      240
Complement number system      60
Complement of a logic expression      246
Complementary MOS circuits      114
Complete set      363
Complete sum      274
Complete test set      1043
Complex PLD      37 411
Complex programmable logic device      1005
Component declaration      337
Component library      1035
Component location      1036
Component model      1037
Component statement      336
Component type      1035
Component value      1035
Computer-aided design      30 1033
Computer-aided engineering      1033
Computing the radix complement      61
Concatenation operator      329
Concurrent signal-assignment statement      341
Concurrent statement      336
Condition input      868
Conditional signal-assignment statement      341
Configurable logic block      1017
Connection flag      1036
Consensus      244 294
Consensus theorem      244
Constant      326
Constant declaration      326
Constraints      318
Contact bounce      777
Control unit      867
Controllability      1043
Core logic      210
Counter      804
Cover      244 273
Covering theorem      244
CPLD      37 411 1005
CRC code      92
Critical race      712
Critical signal paths      1040
CS      974
CS-controlled write      989
Cube representation      284
Current flow      135
Current spikes      142
Current-mode logic      215
Custom LSI      39
Cut off      186
Cut set      709
Cyclic-redundancy-check code      92
D latch      631
d-set      279
Data hold time      989
Data output      960
Data setup time      989
Data sheet      126
Data unit      867
Dataflow description      341
Dataflow design      341
dc      310
DC balance      99
DC fanout      140
DC load      131
DC noise margin      131 195
de Morgan’s theorems      245
Dead time      451
Deasserted      376
Debounce      777
Decade counter      810
Decimal decoder      416
Decimal-to-radix-r conversion      54
Decision window      886
Decode      414
Decoder      87 413
Decoding      87
Decoupling capacitors      143
Delay      390
Delta-delay      353
Demultiplexer      472
Design flow      315
Design for testability      1042
Design review      1035
Design-rule checker      1038
Device      300
DFT      1042
Diagnostic test      1042
Die      34
Differential amplifier      216
Differential inputs      217
Differential outputs      217
Digital      23
Digital attenuator      979
Digital logic      108
Digital phase-locked loop      98
Digital telephony      832
Diminished radix-complement system      63
Diode action      180
Diode AND gate      192
Diode breakdown      181
Diode logic      179
Diode-drop      182
DIP package      34
DIP switch      777
Diphase code      100
Directed arc      650
Distance      84
Distinguished 1-cell      274 282
Divide-by-m counter      804
Division overflow      73
Don’t-care bit      84 279
Don’t-care unclocked assignment operator      310
Double-buffered data      836
Down to      326
DPLL      98
Drain      115
DRAM      983 997
Dual in-line-pin package      34
Dual of a logic expression      248
Duty cycle      620
Dynamic hazard      296
Dynamic power dissipation      153
Dynamic RAM      983 997
Dynamic range      978
Dynamic-input indicator      633
ECL      215
ECL 100K family      222
ECL 10H family      219
ECL 10K      219
Eclipse      275
Edge-triggered J-K flip-flop      641
EDO DRAM      1003
EEPROM      972
Electrical characteristics      206
Electrically erasable PLD      411
Electrically erasable programmable read-only memory      972
Electrostatic discharge      143
Element-type      328
else      341 347
Elsif      347
Emitter      185
Emitter-coupled logic      215
EN      636
Enable input      414 636
Encoder      440
END      301
End-around carry      69

Engineering design margins      125
Entity      319
Entity declaration      321
Entity-name      322
Enumerated type      324
EPLD      409
EPROM      971
Equality      497
Equation block      304
Equations      300
EQUIVALENCE      479
Equivalent load circuit      146
Equivalent states      664
Erasable programmable logic device      409
Erasable programmable read-only memory      971
Error      84
Error correction      87
Error model      85
Error-correcting code      88
Error-correcting decoder      91
Error-detecting code      85
ESD      143
Essential hazard      728
Essential prime implicant      274 282
Even-parity circuit      481
Even-parity code      86
Event attribute      749 790
Event list      353
Excess- $2^{m-1}$ system      64
Excess-3 code      76
Excess-B representation      64
Excitation      648
Excitation equation      648 706
Excitation maps      671
Excitation table      658
Exclusive NOR      479
Exclusive OR      479
Exclusive OR gate      362
Exit statement      349
Expression      240
Extended-data-out DRAM      1003
External feedback      802
f      887
Failure      84
Failure rate      1050
Fall time      145
FALSE      324
Fan-in      120
Fanout      140 196
Fast CMOS      177
Fast TTL      204
FB      1006
FCC Part 15      1041
FCT      176
FCT-T      177
Feedback input      802
Feedback sequential circuit      621
Ferroelectric RAM      984
Field      1035
Field-programmable gate array      33 38 411 1016
FIFO      1027
Fighting      165 450
Filtering capacitors      143
Fine line      40
Finite field      845
Finite induction      244
Finite-memory machine      761
Finite-state machines      620
First-in, first-out memories      1027
Fitter      318 924
Fitting      318
Fixed-OR element      403
Flash EPROM      972
Flash memory      972
Flip-flop      28 625
Floating input      142
Floating state      157
Floating-gate MOS transistor      410 971
Floor plan      1040
Flow table      713
FOE      403
For loop      349
Formal parameters      329
Forward resistance      182
Forward-biased diode      181
FPGA      33 38 411 1016
Frame      834
Free-running counter      809
Full adder      501
Full subtracter      503
Function      329
Function declaration      336
Function definition      329
Function hazard      816
Function table      419
Functional block      1006
Functional verification      318
Fundamental-mode circuit      705
Fuse      398
Fusible link      408 971
Gain      187
GAL16V8      405
GAL16V8C      405
GAL20V8      407
Gate      27 115
Gate array      40
Gating the clock      879
Generalized de Morgan’s theorem      246
Generalized Shannon-expansion theorems      362
Generate statement      338 526
Generic array logic device      405
Generic constant      339
Generic declaration      339
Generic map      339
Glitch      292
Go/no-go test      1041
GOTO statement      734
Gray code      78
Group-carry lookahead      512
Group-ripple adder      509
Half adder      501
Hamming code      88
Hamming distance      84
Hardware description language      26
Hardware model      1039
Hazard      292
Hazard-free excitation logic      718
HC      169
HCT      169
HDL      26
Helper output      428
Hexadecimal addition      58
Hexadecimal number system      51
Hi-Z state      157
High-impedance state      157
High-order      50 51
High-speed CMOS      169
High-speed TTL      203
HIGH-state fanout      140 197
HIGH-state unit load      197
HM62256      991
HM6264      991
HM628128      991
HM628512      991
Hold time      632
Hold-time margin      771
Hysteresis      156 452
I/O block      1012 1021
I/O pin      404
IC      32 113

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