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Martin K. — Digital Integrated Circuit Design
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Íàçâàíèå: Digital Integrated Circuit DesignÀâòîð: Martin K. Àííîòàöèÿ: The impact of digital integrated circuits on our modern society has been pervasive. They are the enabling technology of the current computer and information-technology revolution. This is largely true because of the immense amount of signal and computer processing that can be realized in a single integrated circuit; modern IC's may contain millions of logic gates. This text book is intended to take a reader having only a minimal background and knowledge in electronics to the point where they can design state-of-the-art digital integrated circuits.
ßçûê: Ðóáðèêà: Òåõíîëîãèÿ /Ñòàòóñ ïðåäìåòíîãî óêàçàòåëÿ: Ãîòîâ óêàçàòåëü ñ íîìåðàìè ñòðàíèö ed2k: ed2k stats Ãîä èçäàíèÿ: 2000Êîëè÷åñòâî ñòðàíèö: 543Äîáàâëåíà â êàòàëîã: 16.03.2007Îïåðàöèè: Ïîëîæèòü íà ïîëêó |
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Junction capacitance, MOS circuits 261—264 Junction capacitance, reverse-bias diode 74 Junctions, forward-biased junctions 83—85 Junctions, graded junctions 78—79 Junctions, implanting 44—45 Large-signal capacitance 80—81 Large-signal modeling, BJT transistors 113—114 Large-signal modeling, MOS transistors 95—97 Latch-up 106—108 200 Latches, biphase 290 344 Latches, current-mode logic latches 344 Latches, dynamic CMOS latches 293—294 Latches, inverted 286 Latches, static CMOS digital latches 285—291 Layout CMOS 48—59 LDD see "Lightly doped drain transistor" Leakage currents, MOS transistors 106 Leakage currents, transmission gates 247 Level-boosted word lines 463—464 Level-sensitive scan design (LSSD) 512—517 LFSR see "Maximal-length linear-feedback shift register" Lightly doped drain (LDD) transistor 55—61 Linear-feedback shift register (LFSR) 518—521 Lockout 407 Logic family, delay times 23—24 Logic family, noise margins 22—23 Logic family, rise and Call time 23—24 Logic family, threshold voltage 21—22 Logic gales, acyclic 284 Logic gales, BiCMOS 351—355 Logic gales, BiCMOS differential cascade-voltage-switch logic gate (DCVSL) 357 Logic gales, bipolar 324—325 Logic gales, CMOS 8—14 22 169 252—256 Logic gales, current-mode logic gales 335—344 Logic gales, cyclic 284 Logic gales, Domino logic gales 373—377 Logic gales, dynamic gates 500—502 Logic gales, emitter-coupled logic gates 325—333 Logic gales, gate capacitance 260—271 Logic gales, MOS 169 260—274 Logic gales, NMOS 2—8 86 169 183 Logic gales, pseudo-NMOS 169 183—184 Logic gales, synchronous 284 Logic gales, transient response 25—29 Logic gales, transmission gates 2 37—252 Logic, acyclic 427 512 513 LSSD see "Level-sensitive scan design" Mask-programmed ROM 464—467 Masking 37 40 Masks, layout 49—51 Master clock distribution, synchronous logic circuits 309—312 Master-slave flip-flop 346 511 Maximal-length linear-feedback shift register (LFSR) 518—521 Maximum-length sequence generator 407 Memory cells, dynamic RAM 459—460 Memory cells, four-transistor memory cell 442 Memory cells, sensing OM cells 467—470 Memory cells, static RAM 440—452 Memory, address buffers 452—455 Memory, decoders 438 452—455 Memory, dynamic random-access memory (DRAM) 458—464 Memory, electrically programmable ROM (BPROM) 438 465 471—475 Memory, random-access memory (RAM) 291—293 437 438 438—452 457—464 Memory, read-only memory (ROM) 437 438 464—478 Memory, sequential memory 437 Memory, static random-access memory (SRAM) 291—293 438—452 457—458 Memory, writable ROM (WROM) 465 MESFBTs, alloys 485 MESFBTs, back-gating 489 MESFBTs, buffered-FET logic (BFL) 491—493 503 MESFBTs, capacitively coupled Domino logic (CCDL) 500—502 MESFBTs, capacitively enhanced logic (CEL) 493—495 503 MESFBTs, direct-coupled logic (DCL) 495—498 503 MESFBTs, dynamic logic gates 500—502 MESFBTs, hysteresis 489—490 MESFBTs, modeling 487—489 MESFBTs, Schottky metal 485 MESFBTs, second-order effects 489—490 MESFBTs, source-coupled logic (SCL) 498—500 503 MESFBTs, two-phase dynamic FFT logic (TDFL) 500—503 Miller capacitor 140 Minority charge 114 Mixed-mode microcircuits, processing 47 MNMOS transistors 478 Modeling, bipolar-junction transistors (BJT) 69—71 113—114 116—118 148—155 167—168 Modeling, constants 163 Modeling, diodes 126—127 163—164 Modeling, MESFETs 487—489 Modeling, MOS transistors 66—69 95—97 100—108 133—145 164—166 Modeling, RC ladder structure 267—270 Moderate inversion 95 Modified Booth multipliers 422—426 MOS circuits, delay in 260—274 MOS circuits, gate capacitance 260—261 MOS circuits, interconnect capacitance 265—267 MOS circuits, junction capacitance 261—264 MOS design 169 MOS design, CMOS gate design 212—220 MOS design, CMOS logic 169 200—212 MOS design, pseudo-NMOS logic 169—181 196 MOS design, pseudo-NMOS logic gates 169 183—184 187 191 MOS design, SPICE simulations 220—229 MOS design, transistor equivalency 184—200 MOS logic gates 169 260—274 MOS modeling, large-signal modeling 95—97 MOS modeling, latch-up 106—108 MOS modeling, leakage currents 106 MOS modeling, scaling 102—104 MOS modeling, short-channel effects 104—105 MOS modeling, small-signal modeling 100—101 133—145 MOS modeling, subthreshold operation 105—106 MOS transistors 86—87 MOS transistors, body effect 98—99 130 MOS transistors, depletion transistors 86 88 99 MOS transistors, large-signal modeling 95—97 MOS transistors, latch-up 106—108 MOS transistors, leakage currents 106 MOS transistors, modeling 66—69 95—97 100—108 133—145 164—166 MOS transistors, n-channel transistors 86—87 88 98 100 MOS transistors, operation 89—95 MOS transistors, p-channel transistors 88 99 MOS transistors, small-signal modeling 100—101 133—145 164 165 175 MOS transistors, SPICE modeling parameters 119—120 MOS transistors, subthreshold region 105—106 MOS transistors, symbols for 88—89 MOS transistors, threshold voltage 128—130 MOS transistors, triode region 164 MOS transistors, triode relationship 130—133 Multiple-output Domino logic gates 376—377 Multiplexors 398—400 Multipliers see "Digital multipliers" n-channel transistors 66 67 n-channel transistors, MOS transistors 86—87 88 98 100 n-channel transistors, pass transistors 245 n-channel transistors, transmission gale 237 238 n-channel transistors, X gates 242 n-channel X gates, logic 246—247 n-channel X gates, voltage drop 242—246 Nagel, Dr.L. 15 NAND architecture, EPROMs 475—477 nand gate, CMOS 12 nand gate, NMOS 5—6 Native transistor threshold voltage 129 Negative photoresist 38 NMOS depletion-load transistors 198—200 NMOS logic 183 198 199 NMOS logic gates 2—8 86 169 183 NMOS logic gates, logic functions 190—194 NMOS logic with depletion-load transistors 198—200 No-race (NORA) logic 377—380 No-race (NORA) logic, differential NORA logic 390 Noise margins 22—23 nor gate, CMOS 11 npn bipolar transistors 69 On-chip inductors 486—487 Output circuits 275 p-channel transistors 66 67 p-channel transistors, MOS transistors 88 99 p-channel transistors, pseudo-NMOS logic 170—171 p-channel transistors, symbols for 88—89 P-SPICE 15 Parallel termination 332 Parasitic bipolar transistor 107 Parasitic capacitance, bonding pads 278 Parasitic capacitance, SPICE modeling 120 Pass transistor 237 photolithography 36 photoresist 38 40 45 Pinch-off 93 95—96 Pipelined systems, synchronous logic circuits 305—306 Plas see "Programmable logic arrays" Pn junction 72 pnp bipolar transistors 69 Polysilicon gate 87 128 Polysilicon gate, formation 43—44 Polysilicon gate, layout 49—51 Positive photoresist 38 40 Power dissipation, CMOS inverter 209—212 Power dissipation, pseudo-NMOS gates 195—197 367 Power-delay product 103 Programmable logic arrays (PLAs) 427 Programmable logic arrays (PLAs), pseudo-NMOS PLAs 427—429 Programmable logic arrays (PLAs), self-timed dynamic PLAs 429—431 Programmable logic arrays (PLAs), two-phase PLAs 431—433 Programmable Read-only Memory (PROM) 470—475 Programmable read-only memory (PROM), electrically erasable EPROMs (EEPROMs) 474—475 477 Programmable read-only memory (PROM), electrically programmable (EPROM) 438 465 471—475 Programmable read-only memory (PROM), flash EPROMs 474 475 477 Propagate function 410 Pseudo-NMOS inverter 171—172 Pseudo-NMOS inverter, fall lime 180—182 Pseudo-NMOS inverter, gate threshold voltage 175—178 Pseudo-NMOS inverter, rise time 179—180 Pseudo-NMOS inverter, small-signal modeling 175—177 Pseudo-NMOS inverter, transient response 179 Pseudo-NMOS inverters, SPICE simulations 178 220—225 Pseudo-NMOS loads 365—367 398 Pseudo-NMOS logic 169—182 196 453 Pseudo-NMOS logic gates 169 183—184 187 191—197 Pseudo-NMOS logic gates, bias voltage 197 Pseudo-NMOS logic gates, complex 191—192 Pseudo-NMOS logic gates, power dissipation 195—197 367 Pseudo-NMOS logic gates, transistor size 195 Pseudo-NMOS logic, disadvantages 366 367 Pseudo-NMOS PLAs 427—429 Pseudo-random noise generator 407 Q-factors 511 Q-V curve 76 Quasi constant scaling 104 RAM see "Random access memory" Random access memory (RAM), dynamic (DRAM) 458—463 Random access memory (RAM), static (SRAM) 291—293 438—452 457—458 Random-access LSSD 518 Random-access scan 518 Ratioed gates 11 511 Ratioless gates 11 RC approximate modeling, transient responses 29—31 260 RC ladder structure 267—270 Reactive ion etching (RIE) 59 Reactive plasma etching 44 Read-only memory (ROM) 464—465 Read-only memory (ROM), charge pumps 477—478 Read-only memory (ROM), electrically programmable ROM (EPROM) 438 465 471—475 Read-only memory (ROM), fusible-link ROM 465 Read-only memory (ROM), mask-programmed ROM 464—467 Read-only memory (ROM), NAND architecture 475—477 Read-only memory (ROM), programmable read-only memory (PROM) 470—475 Read-only memory (ROM), writable ROM (WROM) 465 Regenerative differential logic 390—393 Register-based controllers 317—320 Resistor equivalency 188—189 Reverse-biased diodes 74—78 Reverse-biased diodes, modeling equations 163 RIE see "Reactive ion etching" Ripple counter 405 Ripple-carry adder 339 Ripple-carry adders 412 Rise and fall time 23—24 Rise time 23—24 Rise time, pseudo-NMOS inverter 179—180 Row decoder 439 Saturation region 94 SBFL see "Superbuffer FET logic" Scale current 112 Scaling, MOS transistors 102—104 Scan-design techniques 511—518 Scan-path design 517 Scan/Set testing 517—518 Schottky diodes 72 85—86 Schottky diodes, GaAs digital circuits 486 SCL see "Source-coupled logic" Second-order effects, MESFETs 489—490 Self-timed dynamic PLAs 429—431 Semiconductors, defined 71 Semiconductors, diodes 72—74 Semiconductors, forward-biased junctions 93—95 Semiconductors, graded junctions 78—79 Semiconductors, large-signal junction capacitance 80—83 Semiconductors, reversed-biased diodes 74—78 Semiconductors, Schottky diodes 72 85—86 Sense amplifier, DRAM 461—463 Sense amplifier, SRAM 449—452 Sensing read-only memory 467—470 Sequential memory 437 Serial-carry counter 406 Series resistance 118 Series termination 332 Shared junction 53 54 Short-channel effects 97 Short-channel effects, MOS transistors 104—105 Sidewall capacitance 262 Signature analysis 518 521—522 Silicon JFETs 487—489 Silicon wafer, fabrication 36 Silicon-controlled rectifier (SCR) 107 Simulation 14—19 Single-bit adders 408—412 Single-ended current-mode logic 346—349 Single-phase dynamic logic 380—382 Single-sided diode 75 Small-signal modeling, active region 165—166 Small-signal modeling, bipolar-junction transistors (BJT) 116—118 148—155 Small-signal modeling, CMOS inverter 202—204 Small-signal modeling, forward-biased diode 126—127 Small-signal modeling, MOS transistors 100—101 133—145 164 165 175 Small-signal modeling, pseudo-NMOS inverter 175—177 Source capacitance 140 Source-coupled logic (SCL) 498—500 503 spacer 48 SPICE simulations 15—19 53 SPICE simulations, capacitance 273—274 SPICE simulations, carry-generate circuits 341—342 SPICE simulations, CML carry-generate circuit 358 SPICE simulations, CML latch 359—360 SPICE simulations, CMOS inverter 199 225—229 SPICE simulations, H-SPICE 15 119 SPICE simulations, memory cell 448—449 SPICE simulations, modeling parameters 118—122 SPICE simulations, MOS transistors 176n SPICE simulations, n-chunnel transistor 97—98 156—158
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