Àâòîðèçàöèÿ
Ïîèñê ïî óêàçàòåëÿì
Martin K. — Digital Integrated Circuit Design
Îáñóäèòå êíèãó íà íàó÷íîì ôîðóìå Íàøëè îïå÷àòêó?
Íàçâàíèå: Digital Integrated Circuit DesignÀâòîð: Martin K. Àííîòàöèÿ: The impact of digital integrated circuits on our modern society has been pervasive. They are the enabling technology of the current computer and information-technology revolution. This is largely true because of the immense amount of signal and computer processing that can be realized in a single integrated circuit; modern IC's may contain millions of logic gates. This text book is intended to take a reader having only a minimal background and knowledge in electronics to the point where they can design state-of-the-art digital integrated circuits.
ßçûê: Ðóáðèêà: Òåõíîëîãèÿ /Ñòàòóñ ïðåäìåòíîãî óêàçàòåëÿ: Ãîòîâ óêàçàòåëü ñ íîìåðàìè ñòðàíèö ed2k: ed2k stats Ãîä èçäàíèÿ: 2000Êîëè÷åñòâî ñòðàíèö: 543Äîáàâëåíà â êàòàëîã: 16.03.2007Îïåðàöèè: Ïîëîæèòü íà ïîëêó |
Ñêîïèðîâàòü ññûëêó äëÿ ôîðóìà | Ñêîïèðîâàòü ID
Ïðåäìåòíûé óêàçàòåëü
Accumulated channel 90 Active masks, layout 49—51 Active region 94 113 Active region equation 95 Active region, base charge storage 114 Active region, gate capacitance 260—261 Active region, small-signal MOS modeling 133—141 165—166 Active regions 49 Acyclic logic 427 512 513 Acyclic logic gates 284 Adders see "Digital adders" Address buffers 452—455 Address decoder 347 Address transition bus (ATBR) 456 Address-transition-detect (ATD) circuits 455—457 Air-bridge interconnect 487 Alloys, MESFETs 485 Anisotropic etch 59—60 annealing 40 46 ATBR see "Address transition bus" ATD circuits see "Address-transition-detect circuits" Automatic test equipment 510 526 Avalanching 104 Back-gating 489 Ballistic transport 4—83 Barrel shifter 403—405 Base charge storage, active region 114 Base charge storage, bipolar-junction transistors (BIT) 148 Base charge storage, saturated transistor 114—116 Base overdrive current 115 Base-transit-timc constant 114 BFL see "Buffered-FET logic" BiCMOS differential cascade-voltage-switch logic gate (DCVSL) 357 BiCMOS inverter 351—352 BiCMOS logic 324 350 BiCMOS logic gales 351—355 BiCMOS proccss 47 BILBO see "Built-in logic-block observation" Biphase latches 290 344 Bipolar logic gates 324—325 Bipolar technology, heterojunction bipolar technology (HBT) 503—505 Bipolar-junction transistors (BJT) 109—110 Bipolar-junction transistors (BJT), base charge storage 114—116 148 Bipolar-junction transistors (BJT), exponential relationship 145—147 Bipolar-junction transistors (BJT), graded junction 78—79 Bipolar-junction transistors (BJT), large-signal modeling 113—114 Bipolar-junction transistors (BJT), modeling 69—71 113—114 116—118 148—155 167—168 Bipolar-junction transistors (BJT), operation 110—112 Bipolar-junction transistors (BJT), processing 48 Bipolar-junction transistors (BJT), small-signal modeling 116—118 Bipolar-junction transistors (BJT), SPICE modeling parameters 120—122 Body effect 98—99 130 199 Body-effect constant 98 130 Bonding pads, parasitic capacitance 278 Boundary-scan testing 526—532 Buffered-FET logic (BFL) 491—493 503 Built-in logic-block observation (BILBO) 522—526 Built-in self test (BIST) 518 523 Butting contact 56 Capacitively coupled Domino logic (CCDL) 500—502 Capacitively enhanced logic (CEL) 493—495 503 Capacitors, GaAs digital circuits 486 Carry-generate function 339 Carry-lookahead adders 414 Carry-lookahead counter 406 Carry-propagate adders 415 Carry-save adders 412—414 426 Carry-select adders 414 415 CCDL see "Capacitively coupled Domino logic" Cel see "Capacitively enhanced logic" Channel-length modulation 96 136 Charge pumps, EPROM circuits 477—478 Charge sharing, Domino logic gates 374—376 Charge-pump driver 463 Chemical vapor deposition (CVD) 40 CiCMOS process 350 351 Clock latch 240—241 Clock-feedthrough, transmission gates 248—252 Clocked inverter 293 Clocked latches, CMOS 285—294 Clocks, level-sensitive scan design (LSSD) and 514—516 CMOS circuits 86 CMOS circuits, differential-logic design 252—256 CMOS clocked latches 285—294 CMOS flip-flops 301—304 CMOS Inverter 200—201 CMOS inverter, design 364—393 CMOS inverter, rise and fall time 23—24 CMOS inverter, small-signal modeling 202—204 CMOS inverter, SPICE simulations 199 225—229 CMOS Inverter, threshold voltage 201—202 CMOS Inverter, transient response 204—209 CMOS logic 169 200—212 350 CMOS logic gates 8—14 22 169 CMOS logic gates, delay 270—272 CMOS logic gates, design 212—220 252—256 CMOS logic gates, noise margin 22 CMOS logic, design 364—393 CMOS logic, differential CMOS 382 384—388 CMOS transistors, layout and design 48—59 CMOS transistors, processing 35—47 59—61 CMOS transmission gates 245 Combinatorial logic 512 Computer simulation 14—19 Conditional-carry adders 418 Constant, field scaling 102 103 Constant-voltage scaling 104 Contact holes, opening 46 Contact masks, layout 50 Counters 405—408 Current-mode logic (CML) 327 333 334—335 Current-mode logic (CML), buffers 349—350 Current-mode logic (CML), differential-to-single-ended conversion 346—349 Current-mode logic (CML), flip-flops 346 Current-mode logic (CML), latches 344 Current-mode logic buffers 349—350 Current-mode logic flip-flops 346 Current-mode logic gates 335—344 Current-mode logic latch 344 Curtice model 489 Cutoff region, small-signal MOS modeling 141—145 CVD see "Chemical vapor deposition" Cyclic logic gates 284 Czochralski method 36 D flip-flop 295—296 511 Data mode 512 DCL see "Direct-coupled logic" DCVSL see "Differential cascade-voltage-switch logic gate" de Morgan's theorem 338 Decoders 400—403 438 452—455 Delay time 23—24 Delay, CMOS logic gates 270—272 Delay, MOS circuits 260—274 Delay, RC ladder structure 267—270 Depletion capacitance 74 76 79 153 Depletion transistors 86 88 99 Depletion-load transistors, NMOS logic 198—200 DIBL see "Drain-induced barrier lowering" Differential cascade-voltage-switch logic gate (DCVSL) 357 Differential CMOS 382 384—388 Differential current-mode logic 346—349 Differential NORA logic 390 Differential split-level (DSL) CMOS logic 385—387 Differential-logic design 252 Differential-logic design, CMOS circuits 252—256 Diffusion capacitance 84 153 Diffusion capacitance, diodes 125—126 Diffusion implantation 38 Digital adders 408 Digital adders, carry-lookahead adders 414 Digital adders, carry-propagate adders 415 Digital adders, carry-save adders 412—414 426 Digital adders, carry-select adders 414 415 Digital adders, conditional-carry adders 418 Digital adders, full adder 338 339 408 Digital adders, ripple-carry adders 412 Digital adders, single-bit adders 408—412 Digital latch 285 Digital latch, current-mode logic latch 344 Digital latch, static CMOS digital latch 285—291 Digital multipliers 419—426 Digital subtractors 418—419 Diode-connected transistors 367 429 Diodes, diffusion capacitance 125—126 Diodes, exponential relationship 122—125 Diodes, forward-biased diode 126—127 163—164 Diodes, modeling 126—127 163—164 Diodes, reverse-biased diodes 74—78 163 Diodes, Schottky diodes 72 85—86 Diodes, single-sided diode 75 Diodes, SPICE modeling parameters 118—119 Direct-coupled logic (DCL) 495—498 503 Direct-path current 211 DML see "Current-mode logic" Domino logic gates 373 374 Domino logic gates, charge sharing 374—376 Domino logic gates, multiple-output 376—377 Domino logic, capacitively coupled Domino logic (CCDL) 500—502 Domino-CMOS logic 368 370—377 Domino-CMOS logic without inverters 373—374 Domino-CMOS logic, charge sharing of Domino logic gates 374—376 Domino-CMOS logic, multiple-output Domino logic circuits 376—377 Domino-CMOS logic, static 374 Donors 71 Dopants 71 Double-polysilicon process 442 Drain side-wall capacitance 140 Drain-induced barrier lowering (DIBL) 105 Drain-lag 489—490 DRAM see "Dynamic random-access memory" Drift 83 Drive transistors 184 187 DSL CMOS logic see "Differential split-level CMOS logic" Dynamic bus equalization 455 Dynamic CMOS latches 293—294 Dynamic FET logic, two-phase see "Two-phase dynamic FET logic" dynamic loads 367—370 398 Dynamic logic gates 500—502 Dynamic precharging 367—370 Dynamic random-access memory (DRAM) 458—464 Dynamic random-access memory (DRAM), level-boosted word lines 463—464 Dynamic random-access memory (DRAM), sense amplifier 461—463 Dynamic random-access memory (DRAM), storage cells 459—460 Dynamic random-access memory sense amplifier 461—463 ECL see "Emitter-coupled logic" Edge detectors 456—457 Edge-triggered SR flip-flop 297—298 EEPROMs see "Electrically erasable EPROMs" Effective gate-source voltage 90 Effective minority earner lifetime 106 Electrically erasable EPROMs (EEPROMs) 474—475 477 Electrically programmable ROM (EPROM) 438 465 471—475 Electron lifetime 106 electron-hole pairs 104 Emission coefficient 118 Emitter-coupled logic (ECL) 327 Emitter-coupled logic gates 325—333 Enhancement MOS transistors 66 EPROM see "Electrically programmable ROM" Etching, anisotropic etch 59—60 Etching, hydrofluoric acid 40 Etching, reactive ion etching 59 Etching, reactive plasma etching 44 Eutectic bonds 46 Exclusive-or function 183 237—239 409—410 456 Exponential relationship, bipolar-junction transistors (BJT) 145—147 Exponential relationship, diodes 122—125 Fall time, pseudo-NMOS inverter 180—182 Fermi potential 129 Field implants 40—41 140 Field oxide 40—42 Finite-field theory 519 Flash EPROMs 474 475 477 Flip-flops 294—295 Flip-flops, CMOS flip-flops 301—304 Flip-flops, current-mode logic flip-flops 346 Flip-flops, D flip-flop 295—296 511 Flip-flops, edge-triggered SR flip-flop 297—298 Flip-flops, JK flip-flop 298—300 304 346 405 511 Flip-flops, master-slave flip-flop 346 511 Flip-flops, SR flip-flop 295 296—297 511 Flip-flops, T flip-flop 301 511 Flip-flops, testing 511 Floating-gate transistor 471—472 Forward-biased diode, junction capacitance 84—85 Forward-biased diode, modeling equations 163—164 Forward-biased diode, small-signal modeling 126—127 164 Forward-biased junctions 83—85 Four-transistor memory cell 442 Fowler — Nordheim tunneling 473 476 477 Full adder 338 339 408 Fusible-link, ROM 465 Gale capacitance, MOS circuits 260—261 Gallium arsenide (GaAs) digital circuits 483—484 Gallium arsenide (GaAs) digital circuits, air-bridge interconnect 487 Gallium arsenide (GaAs) digital circuits, buffered-FET logic (BFL) 491—493 503 Gallium arsenide (GaAs) digital circuits, capacitively coupled Domino logic (CCDL) 500—502 Gallium arsenide (GaAs) digital circuits, capacitively enhanced logic (CEL) 493—495 503 Gallium arsenide (GaAs) digital circuits, capacitors 486 Gallium arsenide (GaAs) digital circuits, direct-coupled logic (DCL) 495—498 503 Gallium arsenide (GaAs) digital circuits, dynamic logic gates 500—502 Gallium arsenide (GaAs) digital circuits, heterojunction bipolar technology (HBT) 503—505 Gallium arsenide (GaAs) digital circuits, MESFETs 484 485 487—491 Gallium arsenide (GaAs) digital circuits, on-chip inductors 486—487 Gallium arsenide (GaAs) digital circuits, Schottky diode 486 Gallium arsenide (GaAs) digital circuits, source-coupled logic (SCL) 498—500 503 Gallium arsenide (GaAs) digital circuits, thin-film resistors 486 Gallium arsenide (GaAs) digital circuits, two-phase dynamic FET logic (TDFL) 500—503 Gate oxide 42 Gate threshold voltage, pseudo-NMOS inverter 175—178 Gate-overlap capacitance 261 generate function 410 Graded junction 78—79 Gray-code counter 313—317 406 H-SPICE 15 119 HEMTs see "High electron mobility transistors" Heterojunction bipolar technology (HBT) 503—505 High electron mobility transistors (HEMTs) 485—486 Hole lifetime 106 Hot-carrier effects 104—106 Hybrid-re model 116 149 Hysteresis, MESFETs 489—490 Impact ionization 104 Indium phosphide 505 Input impedance, MOS logic gate 274 Input-output circuits 274—280 Input-protection circuits 274—275 Integrated injection logic 367n Interconnect capacitance, MOS circuits 265—267 Interconnect metal 46 Intrinsic gate capacitance 261 Intrinsic silicon 71 128 Inverted channel 90 Inverted latches 286 Inverter delay time 23—24 ion implantation 38 44 JK flip-flop 298—300 304 346 405 511 Junction capacitance 43 53 54 68 Junction capacitance, forward-biased diode 84—85 Junction capacitance, large-signal capacitance 80—81
Ðåêëàìà
|
|
Î ïðîåêòå