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| Ïîèñê ïî óêàçàòåëÿì |
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| Dally W.J., Poulton J.W. — Digital Systems Engineering (part 2) |
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| Ïðåäìåòíûé óêàçàòåëü |
1/f noise 292
AC coupling 112—113
Align block 503—508
Align block, implementation 505 506
Align block, quick return 506—508
Alpha panicles 286—288
Alpha panicles, critical charge 287
American Wire Gauge (AWG) 49—51
Amplifier, cascode 194—195
Amplifier, Chappell 543—544
Amplifier, differential 204—206 210—211 543
Amplifier, differential complementary 544
Amplifier, four-input differential summing 369
Amplifier, integrating 545
Amplifier, self biased 543—544
Amplifier, static 542—544 see
Amplitude modulation 74
Antenna gain 73
Aperture offset time 407
Aperture time 184 407
Arbiter 487 499
Arbiter, four phase 494—495
Arbitration 466 487 494—495 498—199
Area bonding 31—32 242—243
Array oscillator 609—610
Asynchronous design 486—510
Asynchronous design, align block 503—507
Asynchronous design, bundler 506
Asynchronous design, composition 502—510
Asynchronous design, cyclic circuit 508—510
Asynchronous design, delay insensitive 500—501
Asynchronous design, matched delay 500—501
Asynchronous design, pipelines 503—508
Asynchronous design, stable state 492
Asynchronous design, state diagrams 492—493
Asynchronous design, trajectory map 495—497
Asynchronous design, transient state 492
Avalanche breakdown 551
backplane 48—49
Balanced termination 111
Ball-grid array 34
Bang-bang control 633
Bazes amplifier 544
Bi-phase modulation 62
Bias generator 561—562
Binary signalling 345
Bipolar signalling 318—319
Bit stuffing 373 414
Bit-error rate (BER) 297—298
Body effect 155—156
Bond-wire inductor 614—615
Bootstrap Clock-AND 190—191
Break-be fore-make action 524
Bundled signalling 412—413
Bundler 506
Burst errors 349—350 377
Burst-error length 377
Bus 106—108
Bus, matched stubs 144—145
Busbars 53—54
Bypass capacitor 223 247—249
Bypass capacitor, equivalent circuit 247—248
Bypass capacitor, hierarchy 248—249
Bypass capacitor, on chip 243—245
Bypass capacitor, sizing 226—228
Bypass capacitor, sizing, for intra-cycle ripple 226—227
Bypass capacitor, sizing, for step response 227—228
Bypass capacitor, symbiotic 237 244—245 see
C-element 501
cabinets 47
Cable 49—54
Cable, signalling 51—53
Capacitance 82—84
Capacitance, coaxial cable 82—83
Capacitance, microstripline 83
Capacitance, Miller effect 89 179—180
Capacitance, parallel-plate 82—83
Capacitance, wire pair 82—83
Capacitor, bypass 247—249 see
Capacitor, effective series resistance (ESR) 247—248
Capacitor, equivalent circuit 247—248
Capacitor, frequency response 248
Cascode 194—195
Cascode current mirror 197—199
Channel-length modulation 154—155
Chappell amplifier 543—544
Charge pump 624—627
Charge pump, charge injection 626—627
Charge pump, differential 627—840
Charge pump, voltage ripple 626—627
Charge sharing 185—186 588—589
Charge sharing, in precharged gates 186
Chassis 47
Choice 494—495 498—580
Circuit analysis, qualitative 210—212
Circuits, transmission 522—540
Clamps 228—230
Clock aligner 635—640
Clock aligner, delay-locked loop 636—640
Clock aligner, dual loop 636—637
Clock aligner, hybrid 639—640
Clock aligner, phase interpolating 638—639
Clock aligner, phase-locked loop 635—636
Clock buffer 603—604
Clock buffer, zero delay 428—430
Clock distribution 9 449—457
Clock distribution, mesh 456—457
Clock distribution, off chip 449—454
Clock distribution, on chip 454—457
Clock distribution, phase locked 451—452
Clock distribution, round trip 453—454
Clock distribution, salphasic 452—453
Clock distribution, trees 450—451 454—456
Clock domain 400 467—468 472—473
Clock enable 580—581
Clock predictor 484
Clock recovery, oversampling 447—M 9
Clock stopper 492—493
Clock stopper, trajectory map 497
Clock, adjustment 569—57!
Clock, input conditioning 607—608
Clock, multiphase 559—560 568—569
Clock, qualified 580—581
Clock, rise-time constraint 586—587
Clock, stoppable 487—488 492—493
Clocked amplifier, transient response 209—210
Clocked amplifiers 207—209 544
Clocked amplifiers, transient response 209
Clocked signalling 412—413
Clocked-storage elements 406—409
Closed-loop timing 9 397 428—449
Closed-loop timing, bundled 436—439
Closed-loop timing, per-line 439—441
CMOS Inverter 170—183
CMOS Inverter, as an amplifier 542—543
CMOS Inverter, asymmetrical sizing 178—179
CMOS Inverter, current profile 237—238
CMOS Inverter, DC transfer characteristics 170—173
CMOS Inverter, delay line 589—590
CMOS Inverter, energy-delay product 213—214
CMOS Inverter, gain 172—173
CMOS Inverter, gain-bandwidth product 180—181
CMOS Inverter, input offset voltage 288—289
CMOS Inverter, input offset voltage, compensation 289—290 542
CMOS Inverter, Miller-effect capacitance 180
CMOS Inverter, noise margin 171
CMOS Inverter, power dissipation 212—214
CMOS Inverter, simulated transfer characteristics 182
CMOS Inverter, threshold voltage 171
CMOS Inverter, transient response 171—179
| CMOS Inverter, tri-state 186
CMOS Inverter, with feedback 284
CMOS, static gate 170—183
Coaxial cable 51—52 83
Code-division multiple access (CDMA) 75 76
Codes, DC-balance 374—379
Codes, DC-balance, 8b/10b 378—379
Codes, DC-balance, non-overlapping 374—375
Codes, DC-balance, running-disparity 375—376
Codes, error correcting 349—350
Codes, framing 377
Codes, thermometer 519 521
Combinational logic 465—466
Common-mode 200
Common-mode impedance 110 111 201
Complementary MOS (CMOS) 154 see
Completion detection 470—471
Completion signal 491
Concurrency 494—495
Connectors 54—62
Connectors, attachment 61—62
Connectors, coaxial 60
Connectors, elasiomeric 57—58
Connectors, fiber-optic 67
Connectors, inter-chassis 58—60
Connectors, interposers 56—57
Connectors, power 58
Connectors, printed-circuit board 55—56
Connectors, printed-circuit board, edge connector 55—56
Connectors, printed-circuit board, flex circuit 56
Connectors, printed-circuit board, pin-in-socket 56
Connectors, ribbon cable 60—61
Connectors, wire harness 58—60
Contamination delay 405
Critical charge 287
Crosstalk 11 262 267—280
Crosstalk, capacitive 268—272 382—383
Crosstalk, capacitive, countermeasures 271—272
Crosstalk, capacitive, domino logic with keeper 269
Crosstalk, capacitive, driven line 269—270
Crosstalk, capacitive, floating line 268
Crosstalk, capacitive, typical values 270—271
Crosstalk, measurement 121—122 131—134
Crosstalk, on-chip 89
Crosstalk, power supply 280
Crosstalk, reverse-channel 371—372
Crosstalk, signal return 278—280
Crosstalk, signal return, receiver 321—322
Crosstalk, signal return, transmitter 317—318
Crosstalk, transmission line 272—278
Crosstalk, transmission line, countermeasures 277—278
Crosstalk, transmission line, far-end 274—276
Crosstalk, transmission line, near-end 274—276
Crosstalk, transmission line, typical coupling coefficients 276—277
Crystal oscillator 610—613
Current mirror 195—199
Current mirror, cascode 197—199
Current mirror, output impedance 196
Current-mode transmission 315
Current-mode transmitter 529—533
Daughter card 48
DC offset 372—373
DC restoration 379
DC transfer characteristics, CMOS inverter 170—173
DC transfer characteristics, differential amplifier 204—205
DC-balance, codes 374—379
DC-balance, codes, 8b/10b 378—379
DC-balance, codes, non-overlapping 374—375
DC-balance, codes, running-disparity 376—377
DC-balance, digital-sum variation (DSV) 374
DC-balance, disparity 374
DC-balanced signalling 372—379
Decoder 238
Delay 401—402
Delay elements 404—405
Delay tine 404—405 589—603
Delay tine, adjustment, current bias 590
Delay tine, adjustment, multiplexer 589—590
Delay tine, adjustment, range 591
Delay tine, adjustment, variable capacitance 590—591
Delay tine, CMOS inverter 589—590
Delay tine, current-starved inverter 590
Delay tine, device matching 602
Delay tine, differential 593—602
Delay tine, differential, adjustable resistor 594—595
Delay tine, differential, adjustment range 596—597
Delay tine, differential, replica bias 595—599
Delay tine, differential, supply rejection 596—598
Delay tine, inverter, power-supply rejection 592—593
Delay tine, inverter, regulated supply 593—601
Delay tine, power supply considerations 600
Delay tine, substrate noise 602—603
Delay tine, variable 436
Delay, contamination 405
Delay, propagation 405
Delay-insensitive circuits 500—502
Delay-locked loop 429—430 559
Delay-locked loop, clock aligner 636—640
Delay-locked loop, digital control 633—635
Delay-locked loop, dual loop 636—637
Delay-locked loop, false lock 639
Delay-locked loop, hybrid 639—640
Delay-locked loop, initialization 631—632
Delay-locked loop, loop filter 629—635
Delay-locked loop, phase interpolating 638—639
Delay-locked loop, turbo mode 632—633
Demodulation, optical 67—68
Demultiplexing receiver 547—548
Dielectric absorption 105—106
Differential amplifier 204—206 211
Differential amplifier, DC transfer characteristics 204—206
Differential amplifier, transient response 206
Differential Cascode Voltage Switch (DCVS), Logic 190
Differential circuits, amplifier 204—2O6 210—212
Differential circuits, analysis 200
Differential circuits, delay line 593—603
Differential circuits, impedance 201
Differential circuits, infinite impedance load 202
Differential circuits, loads 201—203
Differential circuits, mode coupling 202—203
Differential circuits, negative impedance load 202
Differential circuits, offset voltage 290—291
Differential circuits, replica bias 595—599
Differential circuits, source-coupled pair 199—200
Differential loads 201—203
Differential signalling 328—331 389—391
Differential signalling, pulsed 383—385
Differential signalling, simultaneous bidirectional 368—370
Differential-mode 200
Differential-mode impedance 108—109 110—111
Diffusion equation 91
Digitally trimmed resistors 204 518—521 528—529
Diodes, avalanche photodiodes 67—68
Diodes, PIN 67
Directional coupler 122—123
Disparity 374
Domino logic 187—190
Domino logic, dual rail 189—190
Domino logic, dual-rail XOR 189—190
Domino logic, latch 188—189
Dover see “Transmitter circuits”
Dual-inline package 32
Dual-rail signalling 411—412
Duty factor 402
Duty-cycle corrector 606—607
Dynamic charge sharing 185—186
Dynamic charge sharing, in precharged gates 186—187
Dynamic Circuits 184—191
Dynamic Circuits, bootstrap 190—191
Dynamic Circuits, domino logic 187—191
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