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| Zelkowitz M., Yovits M. — Advances in Computers, Volume 40 |
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| Ïðåäìåòíûé óêàçàòåëü |
AbeIson, R.P. 214 223 230 239 254
ABEL, hardware description language 84—89
Abstract OSSAD, for office modeling 214
Action types, of programmer 8—9
Activities perspective, for office modeling 186 190—192
Activity management system, for office modeling 239—240
Actor paradigm, for office modeling 192 194
Adams, D.A. 189 253
Address, for cache access 133
Ade, M. 107 124
Adelson, Beth 2 8 14 19 27—30 34 36 38
Adequacy, office models see also "Office models"
Adequacy, office models, domain 197—198 225—227
Adequacy, office models, representational 198—201 227—234
Ader, M. 195—196 227 249
Adve, S.V. 170 175
AEI models see "Agent-entity-information models"
Agarwal, A. 161—162 168 172 174 175 177
Agent-entity-information models 223—225 227 230—233 239
Agents perspective, for office modeling 186 193—194 216—219
Ahmed, I. 158 176
Aiello, L. 194 216 246 249
Aiken, M. 195 242 254
Aiken, M.W. 193 253
AiMail, for office modeling 239
Akella, J. 77 121
Alewife, cache coherent multiprocessor 162 168
Alexander's criteria, for prototyping 52—54
Alexander, L. 52 63
Alexandrou, D. 116 121
Algorithm, implemented by a prototype 45
Algudady, M.S. 158—159 174 175
Aliases 133
Allen, J.F. 205 249
Alliance CAD tools 91
Allocate transaction, cache 151
Amaravadi, C.S. 181 184 191 193—196 198—199 212 223 227 239 242 249 254
Amble, T. 223 249
AMICAL, for system synthesis 94—95 110
AMS see "Activity management system"
Andriole, S. 52 60 63
Ang, J. 190—191 193 199 214 225 246 250
AnyBoard, for hardware reusability 100 102
APNs see "Augmented Petri nets"
Apon, A.W. 161 178
Application domain 13
Application-Specific Integrated Circuit see "ASIC design"
Applications perspective, for office modeling 187 195—196 221 223
Arbib, M. 235 254
Archibald, J.K. 137—140 142 151 169 171—173 175—176
Architecture, cache coherence impact on 174
Architecture, IOIS 242
Architecture, models 84
Architecture, multistage interconnection network 129 131 156—161 167—168
Architecture, software prototyping and 45
Architecture, three schema 200
Architecture, VHDL and 84
Arnold, J. 77 103 121
ASIC design for CAD frameworks 91—92
ASIC design for FPGA 100 104—108
ASIC design for system synthesis 93—95 97
ASIC design, comparison with 98
ASIC design, extended VHDL and 110—111
Assimilation process 11
Attardi, G. 219 245 251
Atwood, Michsel E. 31 36
Auge, I. 75 121
Augmented Petri nets, for office modeling 207—209 239
Auramaki, E. 192 194 212 248 249
Babcock, J.D.S. 65 103 111 116 121 123
Baer, J.L. 138—139 151 156 159—160 172—174 175—177
Barber, G. 195 219 245 249
Barbic, F. 191 209 230 240 249 253
Barnes, T. 89 123
Barr, A. 196 249
Beacon, as cue of knowledge 9 17—19
Behavioral model, of architecture 84
Bell, C.G. 164 178
Berkane, B. 80 125
Berkeley protocol, cache 146—147 172
Bernal, Marc 245 249 251
Bhide, A. 69 125
Bhuyan, L.N. 155 158 172 174 176 179
Bieber, M. 196 221 225 244 249
Biggerstaff, T.J. 69—70 121
Bikson, T.K. 184 249
Bilsen, G. 121
Birmingham, W.P. 95 121
Bishop, P. 186 251
Bisiani, R. 161—162 168 176
Bit, change 167
Bit, dirty 133
Bit, exclusive 136
Bit, inclusion 160
Bit, modified 136
Bit, ownership 157
Bit, presence 136
Bitar, P. 149 176
Blanchard, F. 195 250
Bleisinger, R. 252
Boehm, B.W. 66 121
Boehm, E. 41 63
Boehm-Davis, Deborah A. 31 34 36
Bolognesi, T. 81 121
Bonar, Jeffrey 29 34 37—38 196 250
BORG board, for hardware reusability 102—103
Borriello, G. 75 122
Borrione, D.D. 98 121
Bots, P.W. 194 220 243
Bottom-up model, program comprehension 17—19 22
Bourquin, P. 75 121
Boyle, P.D. 150 168 176
Bracchi, G. 185 188—189 191 194 198—199 206—207 209 234 248 250
Bracker, L.C. 193 245 252
Bracker, W.E. 193 245 252
Brantley, W.C. 165 178
Brennan, A. 95 121
Breuer, M. 77 123
Brglez, F. 73 124
Briggs, F.A. 129 164 169 176
Brinksma, E. 81 121
Broadcast signals in bus-based protocols 144
Broadcast signals in MIN-based protocols 156—157
Brobst, S.A. 189 192 227 242 252
Brodersen, R. 76 125
Brooks model, of program comprehension 13—14 21 22
Brooks, F.P., Jr. 67 121
Brooks, Ruven 2 4 7 13 34 36
Bruijing, J. 81—82 121
Brunel, J.Y. 75 121
Bucci, G. 68 121
Buck, J. 92 121—122
Budkowski, S. 80 122
Buell, D. 77 103 121
Burns, C. 80 122
Buurman, P. 96 123
C-TODOS, for office modeling 209—212 227 232—234 240
Cache coherence avoidance 159
Cache coherence problem 128—129
Cache coherence protocol, definition 129
Cache coherence, in multiprocessors, architecture, impact on 174
Cache coherence, in multiprocessors, correctness, importance 170—171 174
Cache coherence, in multiprocessors, hardware protocols 134—162
Cache coherence, in multiprocessors, hardware protocols in prototype/commercial machines 161—162
Cache coherence, in multiprocessors, hardware protocols, actions 135
Cache coherence, in multiprocessors, hardware protocols, bus-based 129 130 142
Cache coherence, in multiprocessors, hardware protocols, bus-based, multiple bus-based 155
Cache coherence, in multiprocessors, hardware protocols, bus-based, performance analysis of 172
Cache coherence, in multiprocessors, hardware protocols, bus-based, protocol standardization 152—153 174
Cache coherence, in multiprocessors, hardware protocols, bus-based, transactions for 151
| Cache coherence, in multiprocessors, hardware protocols, bus-based, write-invalidate 144—151
Cache coherence, in multiprocessors, hardware protocols, bus-based, write-update 151—152
Cache coherence, in multiprocessors, hardware protocols, classification by, bus operation 151
Cache coherence, in multiprocessors, hardware protocols, classification by, control scheme 134
Cache coherence, in multiprocessors, hardware protocols, classification by, state 135 137 153 157 158
Cache coherence, in multiprocessors, hardware protocols, crossbar-based 129 130 155—156
Cache coherence, in multiprocessors, hardware protocols, general, Censier and Feautrier 137
Cache coherence, in multiprocessors, hardware protocols, general, full map 137
Cache coherence, in multiprocessors, hardware protocols, general, Tang's 136—137
Cache coherence, in multiprocessors, hardware protocols, general, threebit 140—141
Cache coherence, in multiprocessors, hardware protocols, general, threestate 140
Cache coherence, in multiprocessors, hardware protocols, general, twobit 138—139
Cache coherence, in multiprocessors, hardware protocols, general, twobit, extended 141—142
Cache coherence, in multiprocessors, hardware protocols, general, Yen and Fu 137
Cache coherence, in multiprocessors, hardware protocols, MIN-based 129 131
Cache coherence, in multiprocessors, hardware protocols, MIN-based with added cache memory 159—161
Cache coherence, in multiprocessors, hardware protocols, MIN-based with coherence control bus. 157—159
Cache coherence, in multiprocessors, hardware protocols, MIN-based, ownership 156—157
Cache coherence, in multiprocessors, hardware protocols, MIN-based, software vs. hardware control 167—168
Cache coherence, in multiprocessors, hardware protocols, snoopy 152 172 173
Cache coherence, in multiprocessors, hypercubes and 162—163 175
Cache coherence, in multiprocessors, memory, overview 128—134
Cache coherence, in multiprocessors, performance analysis 170—173 174
Cache coherence, in multiprocessors, requirements for 168—170
Cache coherence, in multiprocessors, research needs 174
Cache coherence, in multiprocessors, software solutions 163—168
Cache coherence, in multiprocessors, software solutions vs. hardware solutions 167—168
Cache coherence, in multiprocessors, software solutions, assisted cache control 164—167
Cache coherence, in multiprocessors, software solutions, controlled caching of shared data 164—165
Cache, address access 133
Cache, characteristics 128
Cache, clean-shared 137
Cache, components 132
Cache, crosspoint 155—156
Cache, defined 131
Cache, global state 137
Cache, inclusion property 156
Cache, local state 137
Cache, memory block policies 132—133
Cache, performance measure 132
Cache, switch 160
Cache, transaction categories 151
Cacheability attribute 165
CAD see "Computer-aided design"
Cadence 92 122
Cadence CAD tools 92
Caerts, C. 122
Cambrosio, A. 195 250
Camurati, P. 80 122
Card, S.K. 196 250
Carlson, S. 82 114 122
Celentano, A. 189 250
Censier, L.M. 136—137 176
Chan, C.F. 74 124
Chan, P.K. 102 122
Chang, A. 192 223 239 250
Chang, S.K. 192 243 250
Charachorloo, K. 161 168 177
Charette, R. 41 63
Chatelain, C. 139 176
Chen, H. 189—190 196 250
Cheng, W. 77 123
Cheong, H. 166—167 176
Cheriton, D.F. 150 168 176
Chi, V. 68 122
Chiodo, M. 75 122
Chou, P. 75 122
Choy, C.S. 74 124
Choy, D.M. 188 246 252
Christie, B. 185 250
chunking 8 17
Chunks, definition 6
Circles, and augmented Petri nets 207
Classification, cache coherence protocols 134—135 137 151 157—158
Clean-shared cache 137
Co-ordinator, for office modeling 240
Code cognition see "Program understanding"
Cognition models see also "Program understanding models
Cognition models, elements 5—10
Cognition models, expert characteristics and 9—10
Cohen, M.D. 189 192 227 242 252
Coherence control 157—159 see
Cokes, for office modeling 240
Collier, C.C. 169 176
Communications perspective, for office modeling 186 192—193 212—214
Competitive snooping protocol, cache 152 172
Computer-aided design, design cycle and 66
Computer-aided design, framework tools 89—93
Conceptual rule language, for office submodeling 206—207
Configuration, and VHDL 84
Configurators, in office modeling 218
Conklin, E.J. 190 250
Conrath, D.W. 185 190—191 193—194 199 214 225 227 246 250 254
Conte, S.D. 69 71 122
Control primes 17
Cook, Curtis R. 9 25 29 31 34 37
Coordination perspective, for office modeling 192-193
Correlational study, program understanding 27—28 30 32
Cost, software development 41
Critical section, parallel programs 164
Croft, B.W. 190—191 193 195—196 212 225 227 247 250 252 255
Crosby, Martha E. 31 36
Cross-referencing 8 17
Crossbar-based protocol, cache 129 130 155—156
Crutchfield, S. 72 80 123
Cunniff, Nancy 31 36
Curtis, Bill 37
Cyre, W. 72 122
Cytron, R. 165 176
D'Ambrosio, G. 75 124
Daelemans, W. 252
Dangling purpose unit 11
Darema-Rogers, F. 164 176
Das, C.R. 127 158—160 174 175 179
DasGupta, S. 69 71 122
DASH, cache coherent multiprocessor 161—162 168
Data perspective, for office modeling 185 188—190 227
Data, cacheability 165
Data, experimental, analysis 24—25
Davies, Simon P. 31 34—35 36—37
Davis, Alan M. 39 43—45 47 49 52 61 63 67 69
Davis, E. 77 103 121
Davis, T. 75 122
De Antonellis, V. 214 246 250
de Jong, P. 218 250
De Micheli, G. 69 71 74 78 122
Dean, J.S. 190 252
Decision structure 221
Decision support system 195
Decisions perspective, for office modeling 187 194—195 220—221
Deep reasoning, and program understanding 8
Definition phase, of experiment 22 24
DeMarco, T. 72 122
Dembinski, P. 80 122
Dengel, A. 252
Desai, S. 185 198—199 250
Descriptive OSSAD, for office modeling 214—216
Design cycle 66
Design prototype 45
Design, critical requirements and 50—52
Design, formalization 70—71
Design, hardware-software codesign 74—75
Design, library of 107—109 110
Design, tools for comparison 98—99
Despain, A.M. 149 176
Detienne, Francoise 29 34 37
Developmental risk 40
Dhar, V. 188—190 196 244 250
Dhaussy, P. 104 122
Digital signal application, reusability tools for 107
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