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Hill F.J., Peterson G.R. — Computer Aided Logical Design with Emphasis on VLSI
Hill F.J., Peterson G.R. — Computer Aided Logical Design with Emphasis on VLSI

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Название: Computer Aided Logical Design with Emphasis on VLSI

Авторы: Hill F.J., Peterson G.R.

Аннотация:

Tied to no particular set of computer-aided logic design tools, it advocates the new emphasis in VLSI design. Includes support of layout synthesis from description in a register transfer level language as well as from design capture. Contains a detailed introduction to Boolean algebra, Karnaugh maps and sequential circuits. In this edition discussion of combination logic has been extended; switching circuits updated; a comprehensive treatment of test generation for VLSI included.


Язык: en

Рубрика: Computer science/

Статус предметного указателя: Готов указатель с номерами страниц

ed2k: ed2k stats

Издание: 4-th edition

Год издания: 1993

Количество страниц: 547

Добавлена в каталог: 31.05.2014

Операции: Положить на полку | Скопировать ссылку для форума | Скопировать ID
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Предметный указатель
Add      340
Adder      200 341
Adder, BCD      183
Adder, binary      200
Adder, carryskip      205 374
Adder, full      201
Adder, half      201 203
Adjacent, logically      90 96
AHPL      317 336 351 373 390 524
Algebra, boolean      32 34 80
Algorithmic state machine      306
All-NAND form      210 380
AND      4 9
AND, vector      325
antisymmetric      41
applicable      399
Arithmetic      20
ASCII      117
ASIC      349
ASM      306
ASM, block      307
ASM, box      306
ASM, chart      306 308
ASM, extended      315 328
Associative      32 37
Asynchronous      416
Back annotation      357 371
Backus — Nauer      353
Base      16
BINARY      16
Binary adder      200
Binary connectives      4
Binary numbers      6
Binary point      18
Binary-coded-decimal      22
Block diagram      9
BNF      353
Boole, George      52
Boolean      32 43 80 524
Boolean algebra      32 34
Boolean differences      463 467
Boolean hypercube      120
Boolean theorems      35
Boundary-scan      480
Branch      307 316
Branch, network      322 342
Branch-and-bound      467
Bus      245 527
BUS, active      244
BUS, CMOS      249
BUS, declared      332
BUS, implied      338
BUS, NMOS      245
BUS, passive      244 338
BUS, precharged      244 336
BUS, tri-state      249
CAD      1 65 341 350
CALD      1 65 387
Canonic      83 84
Carry      21 200
Carry, skip      204 373
Charge sharing      247 383
CIF      350
Class, compatibility      401
Class, equivalence      266 269 272 277
Class, set      518
clock      185 230 236 361
Clock Input Control      311
Clock, control pitfall      312
Clock, mode assumption      237 362
Clock, skew      242
Clock, two phase      243
Closed Collection      404 517
CLUNIT      329 336 527
CMOS      69 71 165 171 180 353 366 472
CMOS, PLA      189
Codes, BCD      22
CODES, conversion      198 318
Codes, error correcting      26
CODES, error detecting      26
Codes, excess-3      23
CODES, gray      23 109
CODES, Hamming      28
CODES, one-hot      322
CODES, seven segment      25 196
Column-multiplicity      496
Combinational logic unit      329 336
Commutative      32
Compatibility Class      401 517
Compatible      399
Complement      39 104
Completely specified      267 276
Computer Aided Design      1
Concatenation      318 324
Conditional connection      331
Conditional transfer      327 329 331
Connection statement      331
Connectives      4 5
Connectives, sufficient sets      12
Consensus      46 145
Consistency search      513
Contact cut      164
Control delay      425 431
control model      313
Control pulse      311
Control sequence      313
Control sequencer      323
Control unit      313
Controllability      478
Controlled Clocking      211 312
Conway      164
Cost      66 136
Counters      265
Counters, up-down      265 280 291
Cover      403
Cover, collection      405
Cover, minimal closed      517
Covered      121
Critical race      483
cterm      338
Cube, Boolean      120
Cube, hyper      120
Cube, sub      121
CYCLE      429
Data transfer      325 327 329
Data unit      313 320
declaration      326
Decoders      93
Decomposition      490 494
Decomposition, charts      173 208 497 500
Decomposition, complex disjoint      499
Decomposition, simple disjoint      494
Deductive      476
Delay      60 177 368
Delay, worst-case      372
DeMorgan's Theorem      12 81 114
Dependency notation      213
Destination set      434
Detected fault      458
Diffusion      68 73 164
Diode      57
Diode transistor logic      57
DIP      62
Disjunctive normal form      83
Distributive      32
Dominate      129
Domino logic      186
Don't-care      106 131 397 408 437 467
Don't-care, absolute      166
Don't-care, application      166 467
Double rail      95 169 177
DTL      57
Duality      33 165
Dummy variable      395
Dynamic hazard      442
Dynamic memory element      243
ECL      60
Edge triggering      240 390
EDIF      341 354 389
Element-list      353 375 389
Emitter coupled logic (ECL)      60
EPROM      199 387
Equivalence, class      266 269 272 277
Equivalence, relational      266
Error, correcting      26
Error, detecting      26
Espresso      144 147 408
Essential hazard      444
Essential prime implicant      100 128 149
Essential PRIMES      147
Essential, relatively      145
Event-driven      360 376
Excited-fault      458 478
Exclusive OR      4 26 181 202 217 233 461
Exitation      234 417
Exitation, map      287 428
expand      147
Extended state table      315
Factoring      209
False-path      372 392
Fan      467
Fan-in      57
Fan-out      57 58
Fan-out, point      461
Fan-out, reconvergent      469 476
fault      456
Fault, coverage      463 468
Fault, detection      458
Fault, grading      475
Fault, propagation      461 478
Fault, simulation      475
Fault, Undetectable      469
Field effect-transistor (FET)      54
Field programmable      152 199
Finite input memory      260
Finite memory      259
Flattening      357
Flip-flop      227 363
Flip-flop, clocked      230
Flip-Flop, CMOS      248 364
Flip-flop, D      231 242
Flip-flop, edge-triggered      240 390
Flip-flop, JK      231 239 286
Flip-flop, master-slave      238 248
Flip-Flop, RS      228 230
Flip-Flop, T      231
Flip-Flop, timing      240
Flow table      419
Flow Table, minimal      424
Flow Table, primitive      419 420
Fork      215
FPGA      387
Full adder      201
Full custom      65 349
Fundamental mode      418 425 441 445
Gal      156
Gate array      183 193 353
Gate Array, programmable      183 193 386
Gate level      359 375
Gates      8 62 64
Gray code      23 109
Hamming code      28
Hardware description language      305 317 359 467
Hasse      41
Hazard      109 439
Hazard, Dynamic      442
Hazard, essential      444
Hazard, Static      109 441
HDL      351
Hexadecimal      19
HPSIM2      326
Huffman Mealy Method      270
Huntington, E.V.      32
Hypercube      120 433
IC      62
Implication graph      521
Implication table      275 402 408 413 423 518
Implied      275 405
inc      335 340
Incompletely specified      105 396
Incompletely specified, function      105
Incompletely specified, sequential circuit      396 406
incr      340
Increment      221 507
Index variable      339
Indistinguishable      266
Integrated circuit      62
Integrated Circuit, custom      65
Integrated Circuit, medium scale      211
Integrated Circuit, package      62
Integrated Circuit, very large scale      54 164
Interative Networks      202 490 506
Intersection      39 147
Inverter      8 56 70 71 186
Inverter, clocked      248
Irredundant      147
JK flip-flop      231 239 286
JTAG      481
Karnaugh map      86 90 94 99 179 205 409
Language      317 353
Latch      229 237
Lattice      42 343
Laws, associative      32 37
Laws, commutative      32
Laws, DeMorgan's      12 26
Laws, distributive      32
LCA      387
Level      311
Level of description      358
Level of gating      94
Level, mode      416
Literal      83 96
Loading      57 58
Logic      1 311
Logic Symbol      9
Lower bound      36
master-slave      238 248
Maximal compatible      401
Maxterm      83
Mead      164
Mealy Model      280
Memory element      229
Memory element, clocked      230
Memory element, CMOS      248
Memory element, dynamic      242
Memory element, edge triggered      240
Memory element, input equation      254 284
Memory element, master-slave      239
Memory element, static      243
Memory, finite      259
Memory, finite input      260
Memory, length      261
Memory, read-only      196 199 309
Meta-stable      363 447
Minimal State      268 273
Minimum distance      27
Minterm      83 340
MIS      221 496
Module      326 526
Moore Model      280
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