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Hill F.J., Peterson G.R. — Computer Aided Logical Design with Emphasis on VLSI
Hill F.J., Peterson G.R. — Computer Aided Logical Design with Emphasis on VLSI



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Название: Computer Aided Logical Design with Emphasis on VLSI

Авторы: Hill F.J., Peterson G.R.

Аннотация:

Tied to no particular set of computer-aided logic design tools, it advocates the new emphasis in VLSI design. Includes support of layout synthesis from description in a register transfer level language as well as from design capture. Contains a detailed introduction to Boolean algebra, Karnaugh maps and sequential circuits. In this edition discussion of combination logic has been extended; switching circuits updated; a comprehensive treatment of test generation for VLSI included.


Язык: en

Рубрика: Computer science/

Статус предметного указателя: Готов указатель с номерами страниц

ed2k: ed2k stats

Издание: 4-th edition

Год издания: 1993

Количество страниц: 547

Добавлена в каталог: 31.05.2014

Операции: Положить на полку | Скопировать ссылку для форума | Скопировать ID
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Предметный указатель
MOS      54 66
MOS, CMOS      69 71 165 171 356
MOS, NMOS      67 69 165 379
MOS, PMOS      69 379
MOSIS      349
MSI      211 349
Multilevel circuits      209 216 221
Multiplexer      181 204 214 215
Multiplicity, column      496
NAND      12 56 59 73 210 369
Negative gate      177
Negative logic      57
Nesting      336
Net-list      353 375 389
Node      353
Noise margin      75
NOR      12 56
Normal term      84
NOT      8
Null set      39
Numbers, BCD      22
Numbers, binary      16
numbers, negative      21
Observability      478
OR      4 9
OR vector      325
Ordering relations      41
Oscillation      363
Overflow      22
Package      62
PAL      153 199
Parity      24 462
Parity, check      24 293
Parity, checker      26 216 218 233 509
Partial ordering      41 383
Partition      266 291 381 403
Partition, closed      291 294
Pass transistor      73 167 177
Patrick's Method      132 144
Pin-list      353
PLA      135 152 189 199
PLA, cost criteria      141
Place-and-route      350 375
PLO      387
PODEM      467
Polysilicon      68 72 73 164
Positive function      168 178
Postulates, Huntington's      32 50
Precedence rule      325
Precharged      185 244
Precharged bus      244 337
Precharged PLA      185
Prime implicant      32 50
Prime Implicant, dominate      129
Prime Implicant, essential      100 128 149
Prime Implicant, secondary essential      131
Primitive flow table      418
Primitives      217 357
probing      456
PRODUCT      83
Product-of-sums      83 104
Programmed Logic      203
Pull-down      70
Pull-up      69
PuLSE      311
Quine — McCluskey algorithm      1 122 144 461
Race      429 445
Race, critical      430 434
Race, non-critical      429
RADIX      16
Read-Only-Memory (ROM)      196 199 309 387
Realization      8 179
Reduce      147
Reduction      324
Redundant      148
Reflexive      41 266
Relation      41 525
Relation, equivalence      41 266
Relation, reflexive      41 266
Relation, symmetric      41 266
Relation, transitive      41 266
Reset state      265
ROM      196 199 309 387
Routing Channel      181 184
ROW-multiplicity      496
RS flip-flop      228 230
RTL      317 335 358 375 513
Saturation      58 68
Scan-path      475 478
secondary      417
Sequential circuit      226 234 253
Sequential Circuit, clock mode      235 237
Sequential Circuit, completely specified      267
Sequential Circuit, controlled clock      211 312
Sequential Circuit, finite-memory      259
Sequential Circuit, fundamental mode      418 425 441 445
Sequential Circuit, general model      234
Sequential Circuit, level-mode      416
Sequential Circuit, Mealy Model      280
Sequential Circuit, Moore Model      280
serial      233
Set theory      39
Setup-time      241 364
Seven Segment Code      25 196
Shannon Claud      133 491
Shannon exclusive-OR theorem      463
Shannon expansion theorem      133 169 464
Shared Row Assignment      433 437
Shift registers      482
Signature register      482
Silver-spoon-law      458
Simulation      352 359 371
Simulation, event-driven      360
Simulation, fault      457
Single Rail      95 169
Single Transition Time      434
Single-fault      469
Speed      60
SPICE      359
Standard Cell      181 193 216 353 367
Standard form      82
State      255 258
State table      255 308 401 406
State Table, completely specified      267
State Table, extended      313 315
State Table, minimal      268 273
State variable      234
State, assignment      284 291
State, diagram      255 265 281 321
State, equivalence      266
State, indistinguishable      266
State, table      255 265 281
State, variable      234
Statement Variable      3
Static hazard      109
Static memory element      243 336
Steering      170
Stuck-at-0      458
Stuck-at-1      459
Stuck-at-fault      458 459 475
Stuck-open      458 472
Sum-of-products      82
Sum-of-Products, minimal      95 100 127
Switch Level      359 379
Switching functions      48
Symbols, logic      9
Symmetric function      490
Symmetric relation      41
synchronizing      362 446
Synchronizing, flip-flop      362
Synchronizing, sequence      265 477 511
Synthesis      2 217 221 255 350 375
Tautology      4 145
template      326
Test, diagnostic      456
Test, fault detection      456
Test, generation      456 461 467 510
Test, sequence      476 513
Test, vector      465
Three State Gate      248
Tools, OCT      490
Tools, software      1
Transfer, conditional      327 329
Transfer, register      325 527
transistor      54 57 164
Transistor, depletion mode      164
Transistor, enhancement mode      164
Transistor, field effect      54
Transistor, pass      73 167 177
Transition list      285
Transition table      254 289 418 427 507
Transitive      41
Transmission gate      73 74 203
TREE      133 148 173
Tree, decoder      196
Tree, freeform      174
Tree, uniform      175
Truth function      3 6
Truth Functional, calculus      4 34
Truth Functional, compound      4
Truth table      4 12
TTL      62 63 356
TTL, Schottky      64
Two Level      94
Two's complement      21
Unate      168 178
Universal set      39
UNKNOWN      361 364 383 467
Up-Down Counter      265 280 291
Upper bound      42
Variable, bound      495
Variable, excitation      234 417
Variable, free      495
Variable, index      339
Variable, secondary      317
Variable, statement      3
Vector      305 524
Vector, operation      323
Vector, Test      465
Venn diagram      39 88
Verilog      351 359
Vertex      120 178
Vertex, focal      178
VHDL      351 359
VLSI      54 164 349 367 371 456
Wangs algorithm      467 510
Yield      456
1 2
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