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Lau J. — Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies
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Название: Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA AssembliesАвтор: Lau J. Аннотация: One-stop, cutting-edge guide to flip chip technologies. Now you can turn to a single, all-encompassing reference for a practical understanding of the fast-developing field that's taking the electronics industry by storm. Low-Cost Flip Chip Technologies, by John H. Lau, brings you up to speed on the economic, design, materials, process,equipment, quality, manufacturing, and reliability issues related to low cost flip chip technologies. This eye-opening overview tells you what you need to know about applying flip chip technologies to direct chip attach(DCA), flip chip on board (FCOB), wafer level chip scale package (WLCSP), and plastic ball grid array (PBGA) package assemblies. You'll discover flip chip problem-solving methods, and learn how to choose a cost-effective design and reliable, high-yield manufacturing process for your interconnect systems as you explore...
*IC trends and packaging technology updates *Over 12 different wafer-bumping methods...more than 100 lead-free solder alloys *Sequential build up PCB with microvias and via-in-pad *How to select underfill materials *And much, much more!
Язык: Рубрика: Технология /Статус предметного указателя: Готов указатель с номерами страниц ed2k: ed2k stats Год издания: 2000Количество страниц: 602Добавлена в каталог: 28.04.2014Операции: Положить на полку |
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Предметный указатель
Thermal resistance of NuBGA 486 493 496—498 500 502—503 Thermal resistance of PCBs 309 Thermal resistance of underfill materials 310 Thermal resistance, effects of air flow on 303—304 Thermal resistance, effects of chip size on 304—305 Thermal resistance, effects of heat sinks on 310—312 313 314 Thermal resistance, FC-BGA package 535—536 Thermal simulation model 527 Thermal-Curing Resin (TCR) 127 Thermogravimetric analysis (TGA) 100 109—110 Thin quad flat pack (TQFP) 10 Thin small outline package (TSOP) 10 12 Thinner substrate 494—496 Three-element rectangular rosette 422 Through-the-hole vias 122 Time domain reflectometer (TDR) 392 466 Time domain transmission (TDT) 466 Time-dependent analysis 326 376—378 Time-dependent creep strain energy density 329 Time-dependent shear creep strain 328 Time-dependent shear stress 327 TMA (thermal mechanical analysis) 100 103—105 Tomographic acoustic microimaging (TAMI) 418 554 560—562 Toshiba, Buried Bump Interconnection Technology ( 143 TQFP (thin quad flat pack) 10 Transfer solder-bump forming process 68 TSOP (thin small outline package) 10 12 Two-sided assembly 408—410 456—462 UBM (under-bump metallurgy) 44 48—49 513 Ultraviolet (UV) light 356 Under-bump metallurgy (UBM) 44 48—49 513 Underfills, curing conditions of 191—193 Underfills, desirable features of 189—190 Underfills, effects on the deformations of SLC substrates 380—385 Underfills, handling and application of 190—191 Underfills, material properties, creep curves 200—201 Underfills, material properties, effects on thermal management of FCOB 309—310 Underfills, material properties, fracture toughness 201—204 Underfills, material properties, moisture content 196—197 Underfills, material properties, storage modulus 194—195 Underfills, material properties, stress-strain relations 199—200 Underfills, material properties, tangent delta and 195—196 Underfills, material properties, TCE values 193—194 Underfills, material properties, Young's modulus 197—198 Underfills, nonuniform and voids 561—562 Underfills, OLGA 518—519 Underfills, passivation and 568 Underfills, shear test of FCOB 206—210 United Microelectronics Corporation (UMC) 364 United States Environmental Protection Agency (USEPA) 98 UV (ultraviolet) light 356 UV-yttrium aluminum garnet (YAG) laser 123 128 130—132 Variously Interconnected Layers (VIL) 142 VCCT (virtual crack closure technique) 435 439 441 442 447—450 VDD (power) conductors 466—467 Via-in-Pad (VIP) 145—146 363 372 Vias see "Microvias" Victor Company of Japan (JVC), Variously Interconnected Layers (VIL) 142 VIL (Variously Interconnected Layers) 142 VIP (via-in-pad) 145—146 363 372 Virtual crack closure technique (VCCT) 435 439 441 442 447—450 Von Mises stress distributions in corner solder joint in flip chip assembly 242 245—250 281 283 Von Mises stress distributions, microvia/VIP substrates and 373—375 Von Mises stress distributions, stress distribution in corner solder joint 326 VSS (ground) conductors 466—467 Wafer bumping with Au 159—160 Wafer bumping with Cu 160—161 Wafer bumping with Ni-Au 161—163 Wafer bumping with solderless materials 89 Wafer bumping with solders, development 43—44 Wafer bumping with solders, electroplating method 47—48 Wafer bumping with solders, evaporation method 44—47 Wafer bumping with solders, fly-through solder jet printing method 58—61 Wafer bumping with solders, microball mounting method 72—78 Wafer bumping with solders, micropunching method 61—67 Wafer bumping with solders, molten solder injection method 67—69 Wafer bumping with solders, solder bumps on AI pads without UBM 84—88 Wafer bumping with solders, solder bumps on PCB method 84 Wafer bumping with solders, solder jet printing method 55—58 Wafer bumping with solders, stencil printing method 50—55 Wafer bumping with solders, SuperSolder method 69—72 73 75 Wafer bumping with solders, Tacky 78—84 Wafer bumping with solders, under-bump metallurgy 48—49 Wafer bumping, Mitsubishi's 63Sn-37Pb solder bumps 521—522 Wafer bumping, OLGA 513—514 Wafer mapping 332 Wafer on wafer (WOW) process 344 345 Wafer-level burn-in (WLBI) 16 Wafer-level chip scale package see "WLCSP" Wafer-level packaging 13—16 Water-soluble flux 517—518 WAVE (Wide Area Vertical Expansion) technology 347—354 Wayne State University 197 Weibull life distribution 463 Wetting behavior 118 Wide Area Vertical Expansion (WAVE) technology 347—354 Wind tunnel experiments 478—490 500—504 Wire bonding chip (face-down) in PBGA packages, described 465—466 Wire bonding chip (face-down) in PBGA packages, new NuBGA package 508 Wire bonding chip (face-down) in PBGA packages, NuBGA design, concepts 466—470 474 Wire bonding chip (face-down) in PBGA packages, NuBGA design, examples 471—474 Wire bonding chip (face-down) in PBGA packages, NuBGA electrical performance 474—478 505—507 Wire bonding chip (face-down) in PBGA packages, NuBGA solder joint reliability 490—492 504 Wire bonding chip (face-down) in PBGA packages, NuBGA standard packages 493—494 Wire bonding chip (face-down) in PBGA packages, NuBGA thermal performance 478—490 Wire bonding chip (face-down) in PBGA packages, thinner substrate and nonuniform heat spreader, NuBGA 494—496 Wire bonding chip (face-up) in PBGA packages, experimental measurements of pop-corning 417—426 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, assembly flow chart 454—456 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, described 452 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, paste, printing, and pick and place 456 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, solder reflow 456 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, surface-mount components 452—454 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, test board 454 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, thermal cycling test and results 462—463 Wire bonding chip (face-up) in PBGA packages, PCB assembly with large PQFP directly on the opposite side, two-sided assembly results 456—462 Wire bonding chip (face-up) in PBGA packages, solder reflow of moisturized PBGAs 427—434 Wire bonding, assembly process 33—34 Wire bonding, compared to solder-bumped flip chips 28—33 Wire bonding, cost of materials 35—43 Wire bonding, described 27 Wire bonding, major equipment requirements 34—35 WLBI (wafer-level burn-in) 16 WLCSP (wafer-level chip scale package), EPS/APTOS, finite element modeling of assemblies 323—324 WLCSP (wafer-level chip scale package), EPS/APTOS, life prediction for corner solder joint 329—330 WLCSP (wafer-level chip scale package), EPS/APTOS, PCB assembly 322—323 WLCSP (wafer-level chip scale package), EPS/APTOS, redistribution and bumping 318—320 WLCSP (wafer-level chip scale package), EPS/APTOS, shear test on board 330 WLCSP (wafer-level chip scale package), EPS/APTOS, solder bump height 320—322 WLCSP (wafer-level chip scale package), EPS/APTOS, solder bump strength 322 WLCSP (wafer-level chip scale package), EPS/APTOS, thermal cycling on board 330 WLCSP (wafer-level chip scale package), EPS/APTOS, time/temperature-dependent creep analysis 324 WLCSP (wafer-level chip scale package), features 317—318 WLCSP (wafer-level chip scale package), FormFactor, 344—347 WLCSP (wafer-level chip scale package), FormFactor, FCOB 345—346 WLCSP (wafer-level chip scale package), omega-CSP, design 339—341 WLCSP (wafer-level chip scale package), Wafer Scale Chip Scale Package (wsCSP), board reliability tests 336—339 WLCSP (wafer-level chip scale package), Wafer Scale Chip Scale Package (wsCSP), design and assembly flow 332—333 WLCSP (wafer-level chip scale package), Wafer Scale Chip Scale Package (wsCSP), features 331—332 WLCSP (wafer-level chip scale package), Wafer Scale Chip Scale Package (wsCSP), package level reliability tests 333—336 WOW (wafer on wafer) process 344 345 X-ray imaging system 556 X-ray techniques 554 YAG (UV-yttrium aluminum garnet) laser 123 128 130—132 Young's modulus of die attach 435 Young's modulus, FCOB with no-flow underfills 224—225 Young's modulus, material properties 197—198 244 Young's modulus, microvia/VIP substrates and 373 Young's modulus, SLC and 382 Young's modulus, temperature-dependent 491
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