High-level synthesis – also called behavioral and architectural-level synthesis –
is a key design technology to realize systems on chip/package of various kinds,
whether single or multi-processors, homogeneous or heterogeneous, for the embedded
systems market or not. Actually, as technology progresses and systems become
increasingly complex, the use of high-level abstractions and synthesis methods
becomes more and more a necessity. Indeed, the productivity of designers increases
with the abstraction level, as demonstrated by practices in both the software and
hardware domains. The use of high-level models allows designers with systems,
rather than circuit, background to be productive, thus matching the trend of industry
which is delivering an increasingly larger number of integrated systems as compared
to integrated circuits.
The potentials of high-level synthesis relate to leaving implementation details
to the design algorithms and tools, including the ability to determine the precise
timing of operations, data transfers, and storage. High-level optimization, coupled
with high-level synthesis, can provide designers with the optimal concurrency structure
for a data flow and corresponding technological constraints, thus providing the
balancing act in the trade-off between latency and resource usage. For complex systems,
the design space exploration, i.e., the systematic search for the Pareto-optimal
points, can only be done by automated high-level synthesis and optimization tools.