Functional verification has become an important aspect of the IC
(Integrated Chip) design process. Significant resources, both in industry and
academia, are devoted to bridge the gap between design complexity and
verification efforts. SAT-based verification techniques have attracted both
industry and academia equally. This book discusses in detail several latest
and interesting SAT-based techniques that have been shown to be scalable in
an industry context. Unlike other books on formal methods that emphasize
theoretical aspects with dense mathematical notation, this book provides
algorithmic and engineering insights into devising scalable approaches for
an effective and robust realization of verification solution. We also describe
specific strengths of the various approaches in regards to their applicability.
This books nicely complements other excellent books on introductory or
advanced formal verification primarily in two aspects:
First, with growing interest in SAT-based approaches for formal
verification, this book attempts to bring various emerging SAT-based
scalable verification techniques and trends under one hood. In the last few
years, several new SAT-based techniques have emerged.