Главная    Ex Libris    Книги    Журналы    Статьи    Серии    Каталог    Wanted    Загрузка    ХудЛит    Справка    Поиск по индексам    Поиск    Форум   
blank
Авторизация

       
blank
Поиск по указателям

blank
blank
blank
Красота
blank
Müller S.M.(ed.), Paul W.J.(ed.) — The Complexity of Simple Computer Architectures
Müller S.M.(ed.), Paul W.J.(ed.) — The Complexity of Simple Computer Architectures

Читать книгу
бесплатно

Скачать книгу с нашего сайта нельзя

Обсудите книгу на научном форуме



Нашли опечатку?
Выделите ее мышкой и нажмите Ctrl+Enter


Название: The Complexity of Simple Computer Architectures

Авторы: Müller S.M.(ed.), Paul W.J.(ed.)

Аннотация:

This book presents a formal model for evaluating the cost effectiveness of computer architectures. The model can cope with a wide range of architectures, from CPU design to parallel supercomputers. To illustrate the formal procedure of trade-off analyses, several non-pipelined design alternatives for the well-known RISC architecture called DLX are analyzed quantitatively. It is formally proved that the interrupt mechanism proposed for the DLX architecture handles nested interrupts correctly. In an appendix all programs to compute the cost and cycle time of the designs described are listed in C code. Running these simple C programs on a PC is sufficient to verify the results presented. The book addresses design professionals and students in computer architecture.


Язык: en

Рубрика: Computer science/

Статус предметного указателя: Готов указатель с номерами страниц

ed2k: ed2k stats

Издание: 1

Год издания: 1995

Количество страниц: 270

Добавлена в каталог: 10.02.2011

Операции: Положить на полку | Скопировать ссылку для форума | Скопировать ID
blank
Предметный указатель
Adder      30—37
Adder, carry look-ahead      34
Adder, comparison      71 123—140 178
Adder, conditional sum      35
Adder, fanout      42
Adder, flags      30 31
Adder, full adder      32
Adder, overflow      30 31
Adder, ripple carry      32
Admissible, control signal      16
Admissible, interrupt service routine      174
Alignment      77
ALU      29 82—86
Architectural module      see “Module”
Architecture      5
Architecture, comparison      7
Architecture, model      5—20
Architecture, performance      6
Architecture, quality      6
Arithmetic logic unit      see “ALU”
Arithmetic unit      38 123
atomic      146
Automaton, Mealy      43
Automaton, Moore      43
Basic component      9
Basic component, n-bit version      21
Benchmark      6 66 133
binary number      23
Branch target computation      78
Buffer      41
Carry look-ahead adder      34
Cause environment      156
Cause processing      157
Cause register      144
Circuit      11 12 15
Clocked circuit      12
Clocking overhead      13
Combinatorial circuit      11
Comparator      83 124
Comparison      5 7 198
Comparison, workload dependent      132
Comparison, workload independent      129
Condition test      83 124—128
Condition test, testing inputs      125
Condition test, two cycles      126
Conditional sum adder      35
Control      15 62 100—110 152
Control circuit, CaPro      157
Control circuit, CM      46
Control circuit, CN      46
Control circuit, MC (memory)      98
Control circuit, NSD      50
Control circuit, NSE      47
Control circuit, OD      45
Control circuit, PCC      97
Control circuit, SPRCon      151
Control circuit, zO      50
Control signals      15 43
Control signals, admissible      16
Control signals, encoding      183 192
Control signals, naming      82
Control signals, standard      112
Control signals, valid      112
Control, automaton      43 157
Control, hardwired      43—58 100
Control, microcoded      179—198
Control, microprogrammed      179—198
Control, parameters      47 106
correctness      173—177
CPI      5 68 133 135
Cycle time      16
Data paths      15
Data paths, DLX      81
Data paths, Markl      61
Data paths, modified hardware      16
Decoder      24
Delay, accumulated      19
Delay, gate      9
Delay, nomenclature      18
Design evaluation      see “Evaluation”
Disjunctive normal form      see “DNF”
DLX      77
DLX control      100—110 152 157
DLX control, DNF      103 106 160
DLX control, FSD      103 158 160
DLX control, microcoded      185—198
DLX control, microprogram      188
DLX control, parameters      106 163
DLX control, signal frequency      106 163
DLX control, signals      101 158 160
DLX data paths      81—100 148
DLX environment, ALU      82—86 123 124
DLX environment, cause      156
DLX environment, instruction register      93
DLX environment, main memory      97—100 148
DLX environment, PC      96 148
DLX environment, register file      94—96
DLX environment, shifter      86—92
DLX environment, special purpose registers      149
DLX, cost      110 164 195
DLX, cycle time      112 166 194 195
DLX, instruction format      77 78
DLX, instruction set      78 106 145
DLX, interrupt      148—172
DLX, simplified view      113 167
DNF      44 103 106 160
Encoder      26
Encoding      see “Control signals”
Environment      81
Equal quality parameter      8
Evaluation      5 63 119 123—140 171 178 196
Exception registers      144
Execution scheme      101
Fanout      22 41 42
Fanout tree      41
Finite state diagram      see “FSD”
Finite state transducer      43
FSD      43 101 103 158 160
FSD, fanin      44
FSD, weight      44
Full adder      32
Functional library      21—42 210—215
Gate delay      9
Gate equivalent      9
Generate signal      35
Half-decoder      26
Hardware model      8—20
Hardware, modified      13
I-type instruction      78
illegal instruction      154 191
Incrementer      28
Input, external      18
Input, open      15
Instruction format      78
Instruction register      93
Instruction set, DLX      see “DLX”
Interrupt      141—178 182
Interrupt convention      143
Interrupt level      173 174
Interrupt service routine      141 145
Interrupt service routine, admissible      174
Interrupt stack      145
Interrupt support      143—164 172
Interrupt support, hardware      144 148
Interrupt support, software      145
Interrupt, caught      173
Interrupt, completion      175
Interrupt, correctness      173—177
Interrupt, event signal      141 153
Interrupt, external      142
Interrupt, finite space      175
Interrupt, maskable      141
Interrupt, nested      145
Interrupt, occurred      173
Interrupt, pending      144 173
Interrupt, precise      175
Interrupt, priority      142 175
Interrupt, receives service      173
Interrupt, response time      174
Interrupt, resume      142
Interrupt, termination      175
Interrupt, type      141
J-type instruction      78
Library, functional      21—42 210—215
Logic unit      84
Main memory      16 97—100 148
Main memory, access time      17
Main memory, control      98
Main memory, modified hardware      17
Main memory, protection      100
Main memory, status signals      17 98 100 154
Main memory, status time      17 121 177
Mark1      59—75
Mark1, cost      63
Mark1, cycle time      64
Mark1, data paths      61
Mark1, instruction set      60
Mark1, quality      68 74
Mealy automaton      43
Mealy implementation      49—53 56
Mealy implementation, binary      49
Mealy implementation, unary      53
Micro state      15
Micro-address selection      181 188
Microcondition      180
Microinstruction      179
Microinstruction format      185
Microprogram      179 188
Microprogram ROM      179
Model, architecture      5—20
Model, hardware      5 8—20
Model, performance      5
Modified hardware      13
Modified hardware, data paths      16
Modified hardware, main memory      17
Modified hardware, RAM      14
Modified hardware, tristate driver      13
Module, architectural      203 222—257
Module, service      203—221 257—262
Moore automaton      43 100
Moore implementation      45—49 54
Moore implementation, binary      45
Moore implementation, unary      48
Motorola H4C technology      9
Number, binary      23
Number, two’s complement      29
Overflow      30 31 154
Parallel prefix      34
Performance      6
Performance model      5
Performance ratio      7
Powerup convention      18
Powerup mechanism      45 50 62 96 148 177 180
Powerup signal      45 156
Propagate signal      35
Protected region      147
q-range, global      135
q-range, local      132
Quality      6
Quality, EQ      8 130
Quality, metric      6
Quality, parameter      6
Quality, ratio      7 74 129
R-type instruction      78
RAM      9
RAM, modified hardware      14
RAM, multiport      10
register      12 22
Register transfer language      43 201—202
Register, general purpose      94
Register, special purpose      144 145 149
Ripple carry, adder      32
Ripple carry, incrementer      28
ROM      10
ROMfac      10 196 198
Sequencing data      180
Service module      see “Module”
Shift, arithmetical      86
Shift, explicit      86
Shift, left      86
Shift, logical      86
Shift, parameters      87
Shift, right      40 86
Shift, special      86
Shifter      86—92
Shifter, barrel      39
Shifter, block diagram      89
Shifter, cyclic      38
Shifter, distance      90
Shifter, fill      90
Shifter, mask      92
Sign extension      77
Status register      144 145 149 151
Status, restore      147 174
Status, save      146 174
Subtraction      37
Table lookup      182 183 190
Technology, Motorola      9
Technology, optimization      41
Technology, Venus      9
Trade-off      69—74 123—140 178
Trap      145 154
Two’s complement number      29
Venus design system      9
Workload      5
Zero test      28
blank
Реклама
blank
blank
HR
@Mail.ru
       © Электронная библиотека попечительского совета мехмата МГУ, 2004-2018
Электронная библиотека мехмата МГУ | Valid HTML 4.01! | Valid CSS! О проекте