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Название: VHDL Coding and Logic Synthesis with SYNOPSYS
Автор: Lee W.F.
In today's world, faster and less costly ASIC chips are being designed at a much quicker rate than before. This requires that ASIC designers be able to design much more efficiently than before. Designers are constantly under pressure to come up with faster performing designs, but with fewer resources. This has led to the development of many EDA tools that help designers to complete a design in a much shorter time frame. These EDA tools are based on the concept of designing ASIC components utilizing Hardware Description Language (HDL). Today, a designer does not need to spend much time manually drawing the circuitry involved in a design but instead can write synthesizable HDL code. A common form of HDL code used in the ASIC industry for synthesis is Very High-Speed Integrated Circuit Hardware Description Language (VHDL) and Verilog. This book discusses only VHDL.