The widely used design rule IPC-2221 (=MIL-STD-275) for the 'current carrying capacity' of traces on printed circuit boards is subject of a closer investigation. These historical studies on correlations between electrical current and temperature rise of the trace can be reproduced by numerical heat transfer simulations only if the board has a back 35μm copper layer and the thickness of the trace is 35 μm. As this makes an extrapolation to other boards impossible, we will present numerical studies for FR4-based board models with other copper planes and also for ceramic substrates. For a better understanding of the results, 2D heat conduction calculations for traces on boards with constant internal and external conditions are performed. Quantitatively, they can be interpreted as parallel thermal resistances of the trace and the rest of the board, where we treat the board approximately as a heat sink fin. These semi-analytic limits give scaling laws for the thermal resistance of the trace as function of board conductivity, heat exchange coefficient, board thickness and trace width. For the more realistic board models this simplified theory is not powerful enough as the thermal isolation between trace and first copper plane is not included.