The combination of previously separate elements into one lone chip presents engineers with challenges to traditional verification approaches. This guide provides a series of tools and techniques that can be employed for system-on-chip (SOC) verification and design error reduction. The authors, who work for Cadence Design Systems, walk through system level and block verification, simulation, hardware/software co-verification, static netlist verification, and physical verification technologies. Particular attention is paid to newer techniques< — >such as testbench migration, formal model and equivalence checking, linting, and code coverage< — >and the material is illustrated by examples based on a Bluetooth SOC design.