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| Patterson D.A., Hennessy J.L. — Computer Organization and Design: The Hardware/Software Interface |
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| Ïðåäìåòíûé óêàçàòåëü |
802.11 standard CD8.3:9—10
absolute addresses A13
Abstractions 21—22 24
Accumulator architectures CD2.19:1—2
Accumulator instructions IMD2:7
acronyms 9—10
ACS CD6.13:4
Activation record 86
Active matrix display 18
Ada 173
Add 49—51 301
add immediate 58
add immediate unsigned 172
add unsigned 172
Adder 292
Addition 170—176
Addition, carry lookahead B38—47
Addition, floating point 197—201
Address (addressing) in large—scale parallel processors CD9.4:23—25
Address (addressing), absolute A13
Address (addressing), base 55
Address (addressing), calculation 385 390 392 402
Address (addressing), exception 342—343
Address (addressing), memory 54
Address (addressing), PC-relative 98
Address (addressing), physical 511 512 513—514
Address (addressing), translation 512 521—524
Address (addressing), virtual 512
Addressing modes, IA-32 138
Addressing modes, MIPS 100
Addressing modes, RISC D5—9
Addressing, MIPS, 32-bit immediate operands 95—96
Addressing, MIPS, branches and jumps 97—99 294—295
Addressing, MIPS, decoding machine language 100—104
Addressing, MIPS, mode summary 100
Advance load 442
Advanced Research Project Agency (AREA) CD7.9:9 CD8.3:5 CD8.11:7
Agarwala, Tilak CD6.13:4
Aho, Al CD2.19:8
Aiken, Howard CD 1.7:3
Air bags 281
Algol CD2.19:6—7
Aliasing 528
Alignment restriction 56
Allan, Fran CD2.19:8
Alpha architecture CD5.12:3 D27—28
Alto 16 CD1.7:7—8 CD7.9:10 CD8.11:7
ALU see Arithmetic logic unit
ALUOp 301—305
ALUOut 319 320 327
AMD 136
AMD Opteron, memory hierarchy 546—550
Amdahl, Gene CD5.12:1
Amdahl’s Law 179 267 494 CD9.2:9 CD9.9:40 IMD4:5—6
and (AND) 70 301 321 B6
AND gate CD3.10:5
and immediate 71
Andreessen, Marc CD8.11:7
Antidependence 439
Antifuse B77
Antilock brakes 281
Apple II CD1.7:5
Application binary interface (ABI) 22
Applications software 11
Archeological sites 236—237
Architectural registers 448
Architecture see Instruction set architecture
Arithmetic logic unit (ALU) 177 179 184 187 201
Arithmetic logic unit (ALU), 1-bit B26—29
Arithmetic logic unit (ALU), 32-bit B29—36
Arithmetic logic unit (ALU), adders and 292 294
Arithmetic logic unit (ALU), ALUOp 301—305
Arithmetic logic unit (ALU), ALUOut 319 320 327
Arithmetic logic unit (ALU), constructing B26—38
Arithmetic logic unit (ALU), control 301—303 C4—8
Arithmetic logic unit (ALU), datapaths and 286 292 294 296
Arithmetic logic unit (ALU), MIPS B32—38
Arithmetic logic unit (ALU), multicycle implementation 318—340
Arithmetic logic unit (ALU), single-cycle implementation 300—318
Arithmetic, Addition 170—176
Arithmetic, division 183—189
Arithmetic, fallacies and pitfalls 220—224
Arithmetic, floating point 189 191—220
Arithmetic, mean 257—258
Arithmetic, Multiplication 176—182
Arithmetic, signed and unsigned numbers 160—170
Arithmetic, subtraction 170—176
Arithmetic-logical instructions 292—293 298
Arithmetic-logical instructions, multiple-cycle implementation 327 329
Arithmetic-logical instructions, single-cycle implementation 300—318
ARM D36—38
ARPANET CD8.3:5 CD8.11:7
Arrays of logic elements B18—19
Arrays, versus pointers 130—134
Art, restoration of 562—563
ASCII (American Standard Code for Information Interchange) 90—91
ASCII (American Standard Code for Information Interchange) versus binary numbers 162
Assembler directives A5
assemblers 13 107—108 A4 10—17
Assembly language 13 107 A3—10 see
Assembly language, disadvantages of A9—10
Assembly language, when to use A7—9
Assert signal 290
Asserted signal 290 B4
Associativity, in caches 499—502
Asynchronous bus 582—583
Asynchronous inputs Â75—77
AT&T Bell Labs CD7.9:8—9
Atanasoff, John CD 1.7:3
Atomic swap operation CD9.3:18
AUocate-on-miss 484
automatic storage class 85
Availability 573
Average Memory Access Time (AMAT) IMD7:1
Bachman, Charles CD8.11:4 5
Backpatching A13
backplane 582
Backus, John CD2.19:6 7
Barrier synchronization CD9.3:15
Base 2 to represent numbers 160—161
Base address 55 100
Base register 55
base stations CD8.3:9
Basic block 75
Basket, Forrest CD7.9:9
Behavioral specification B21
Bell Labs CD7.9:8—9
Benchmarks 254—255
Benchmarks, EEMBC, 255 IMD4:17—18
Benchmarks, kernel CD4.7:2 IMD4:7—8
Benchmarks, SPEC CPU 254—255 259—266 CD4.7:2—3 IMD4:7—8
Benchmarks, SPECweb 99 262—266
Benchmarks, synthetic CD4.7:l—2 IMD4:11—12
Berkeley Computer Corp. (BCC) CD7.9:8 9
Berkeley Software Distribution (BSD) CD7.9:9
Berners—Lee, Tim CD8.11:7
Biased notation 170 194
Big Endian 56 A43
Big-interleaved parity (RAID 3) 576—577
Bigelow, Julian CD1.7:3
Binary digits (numbers) 12 60
Binary digits (numbers), adding and subtracting 170—176
Binary digits (numbers), ASCII versus 162
Binary digits (numbers), converting to decimal floating point 196
Binary digits (numbers), converting to decimals 164
Binary digits (numbers), hexadecimal-binary conversion table 62
Binary digits (numbers), scientific notation 191
Binary digits (numbers), use of 160—161
Binary point 191
bit error rate (BER) CD8.3:9
| Bit(s) 12 60
Bit(s) in a cache 479
Bit(s), dirty 521
Bit(s), fields IMD2:13—14
Bit(s), least significant 161
Bit(s), map 18
Bit(s), most significant 161
Bit(s), reference/use 519
Bit(s), sign 163
Bit(s), sticky 215
Blaauw, Gerrit CD6.13:2
BLNAC CD1.7:4
Block, Barbara 156—157
Block-interleaved parity (RAID 4) 577—578
Blocking assignment B24
Blocks, denned 470
Blocks, finding 540—541
Blocks, locating in caches 502—504
Blocks, placement of 538—540
Blocks, reducing cache misses with 496—502
Blocks, replacing 504 541—542
Bonding 30
Boolean algebra B6
Booth’s algorithm IMD3:5—9
Bounds check shortcut 168
Branch (es), addressing in 97—99 294—295
Branch (es), delay slot 423
Branch (es), delayed 297 382 418—419 A41
Branch (es), history table 421
Branch (es), loop 421—422
Branch (es), multiple-cycle implementation 327—328 336
Branch (es), not taken 295 418
Branch (es), prediction 382 421—423
Branch (es), prediction buffer 421
Branch (es), taken 295
Branch (es), target address 294—296
Branch (es), target buffer 423
Branch equal (beq) 294 297 300—318
Branch/control hazards 379—382 416—424
Branch/control hazards, delayed 297 382 418—419
Branch/control hazards, dynamic branch prediction 421—423
Branch/control hazards, not taken 295 418
Branch/control hazards, untaken 381
Branch/control hazards, Verilog and CD6.7:8—9
Brooks, Fred, Jr. CD6.13:2
Bubble sort 129
Burks, Arthur W., 48 CD1.7:3 CD3.10:1
buses 291—292
Buses, advantages/disadvantages of 581
buses, asynchronous 582—583
Buses, backplane 582
Buses, basics of 581—585
Buses, defined 581 B18—19
Buses, master 594
Buses, Pentium 4 585—587
Buses, processor-memory or I/O 582
Buses, shared 322—324
buses, synchronous 582—583
Buses, transaction 582
bypassing 376—377
Byte addressing 56
byte order A43
C++ CD2.19:7
C, bit fields IMD2:13—14
C, converting floating points to MIPS assembly code 209—213
C, development of CD2.19:7
C, logical operations 68—71
C, overflows 172
C, procedures 81—88
C, sort example 121—129
C, strings 92—93
C, translating hierarchy 106—111
C, while loop in 74—75
Cache coherency, multiprocessor CD9.3:12—20
Cache coherency, protocols CD9.3:13 16—18
Cache coherency, snooping CD9.3:13
Cache coherency, synchronization using CD9.3:18—20
Cache-coherent nonuniform memory access (CC-NUMA) CD9.4:22
Caches, accessing 476—482
Caches, associativity 499—502
Caches, basics of 473—491
Caches, bits in 479
Caches, blocks used to reduce misses 496—502
Caches, blocks, locating in 502—504
Caches, denned 473
Caches, direct-mapped 474—475 497
Caches, example of simple 474—476
Caches, fully associative 497
Caches, Intrinsity FastMATH processor example 485—487
Caches, mapping address to multiword block 480
Caches, memory 20
Caches, memory system design to support 487—491
Caches, misses, handling 482—483 496—502
Caches, multilevel 492 505—510
Caches, nonblocking 445 548
Caches, performance with increased clock rate 495—496
Caches, performance, measuring and improving 492—511
Caches, reducing miss penalty using multilevel 505—509
Caches, set associative 497 504
Caches, split 487
Caches, tags 475 504
Caches, three Cs model 543—545
Caches, valid bit 476
Caches, writes, handling 483—485
Cal TSS CD7.9:8
callee 80 A23
caller 80 A23
Capacity misses 543
Carnegie Mellon University CD6.13:5
Carrier signal CD8.3:8
Carry lookahead B38—47
Carry save adders 181 IMD3:17—18
Case statement 76
cathode ray tubes (CRTs) 18
Cause register 342
Cause Write 342
Central processor unit (CPU) 20
Central processor unit (CPU), execution time 244—245
Central processor unit (CPU), performance 245 246—253
Central processor unit (CPU), time 244—245
Cerf, Vint CD8.11:7
Chamberlin, Donald CD8.11:5
characters, Java 93—95
Chavin de Huantar 236—237
Chips 20 30
Clearing words in memory arrays and 130—132
Clearing words in memory arrays and, comparing both methods 133—134
Clearing words in memory arrays and, pointers and 132—133
Clock cycles 245 B47
Clock cycles per instruction (CPI) 248—251
Clock cycles per instruction (CPI) in multicycle CPU 330—331
Clock cycles, breaking execution into arithmetic-logical instruction 327 329
Clock cycles, breaking execution into branches 327—328
Clock cycles, breaking execution into decode instruction and register fetch 326—327
Clock cycles, breaking execution into fetch instruction 325—326
Clock cycles, breaking execution into jump 328
Clock cycles, breaking execution into memory read 329
Clock cycles, breaking execution into memory reference 327 328
Clock cycles, finite state machines 332
Clock cycles, multicycle implementation 318—340
Clock cycles, single-cycle implementation 300—318
Clock period 245 B47
Clock rate 245
Clock skew B73—74
Clocking methodology 290—292 B47
Clocking methodology, edge-triggered 290—291 B47
Clocking methodology, level-sensitive B74—75
Clocking methodology, tuning methodologies B72—77
clocks B47—49
CLU CD2.19:7
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