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Patterson D.A., Hennessy J.L. Ч Computer Organization and Design: The Hardware/Software Interface
Patterson D.A., Hennessy J.L. Ч Computer Organization and Design: The Hardware/Software Interface

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Ќазвание: Computer Organization and Design: The Hardware/Software Interface

јвторы: Patterson D.A., Hennessy J.L.

јннотаци€:

What's New in the Third Edition, Revised Printing

The same great book gets better! This revised printing features all of the original content along with these additional features:

Х Appendix A (Assemblers, Linkers, and the SPIM Simulator) has been moved from the CD-ROM into the printed book

Х Corrections and bug fixes
Third Edition features

New pedagogical features

ХUnderstanding Program Performance
- Analyzes key performance issues from the programmer's perspective
Х Check Yourself Questions
- Helps students assess their understanding of key points of a section
Х Computers In the Real World
- Illustrates the diversity of applications of computing technology beyond traditional desktop and servers
Х For More Practice
- Provides students with additional problems they can tackle
Х In More Depth
- Presents new information and challenging exercises for the advanced student


язык: en

–убрика: Computer science/

—татус предметного указател€: √отов указатель с номерами страниц

ed2k: ed2k stats

»здание: 3rd edition

√од издани€: 2004

 оличество страниц: 656

ƒобавлена в каталог: 30.06.2009

ќперации: ѕоложить на полку | —копировать ссылку дл€ форума | —копировать ID
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ѕредметный указатель
802.11 standard      CD8.3:9Ч10
absolute addresses      A13
Abstractions      21Ч22 24
Accumulator architectures      CD2.19:1Ч2
Accumulator instructions      IMD2:7
acronyms      9Ч10
ACS      CD6.13:4
Activation record      86
Active matrix display      18
Ada      173
Add      49Ч51 301
add immediate      58
add immediate unsigned      172
add unsigned      172
Adder      292
Addition      170Ч176
Addition, carry lookahead      B38Ч47
Addition, floating point      197Ч201
Address (addressing) in largeЧscale parallel processors      CD9.4:23Ч25
Address (addressing), absolute      A13
Address (addressing), base      55
Address (addressing), calculation      385 390 392 402
Address (addressing), exception      342Ч343
Address (addressing), memory      54
Address (addressing), PC-relative      98
Address (addressing), physical      511 512 513Ч514
Address (addressing), translation      512 521Ч524
Address (addressing), virtual      512
Addressing modes, IA-32      138
Addressing modes, MIPS      100
Addressing modes, RISC      D5Ч9
Addressing, MIPS, 32-bit immediate operands      95Ч96
Addressing, MIPS, branches and jumps      97Ч99 294Ч295
Addressing, MIPS, decoding machine language      100Ч104
Addressing, MIPS, mode summary      100
Advance load      442
Advanced Research Project Agency (AREA)      CD7.9:9 CD8.3:5 CD8.11:7
Agarwala, Tilak      CD6.13:4
Aho, Al      CD2.19:8
Aiken, Howard      CD 1.7:3
Air bags      281
Algol      CD2.19:6Ч7
Aliasing      528
Alignment restriction      56
Allan, Fran      CD2.19:8
Alpha architecture      CD5.12:3 D27Ч28
Alto      16 CD1.7:7Ч8 CD7.9:10 CD8.11:7
ALU      see Arithmetic logic unit
ALUOp      301Ч305
ALUOut      319 320 327
AMD      136
AMD Opteron, memory hierarchy      546Ч550
Amdahl, Gene      CD5.12:1
AmdahlТs Law      179 267 494 CD9.2:9 CD9.9:40 IMD4:5Ч6
and (AND)      70 301 321 B6
AND gate      CD3.10:5
and immediate      71
Andreessen, Marc      CD8.11:7
Antidependence      439
Antifuse      B77
Antilock brakes      281
Apple II      CD1.7:5
Application binary interface (ABI)      22
Applications software      11
Archeological sites      236Ч237
Architectural registers      448
Architecture      see Instruction set architecture
Arithmetic logic unit (ALU)      177 179 184 187 201
Arithmetic logic unit (ALU), 1-bit      B26Ч29
Arithmetic logic unit (ALU), 32-bit      B29Ч36
Arithmetic logic unit (ALU), adders and      292 294
Arithmetic logic unit (ALU), ALUOp      301Ч305
Arithmetic logic unit (ALU), ALUOut      319 320 327
Arithmetic logic unit (ALU), constructing      B26Ч38
Arithmetic logic unit (ALU), control      301Ч303 C4Ч8
Arithmetic logic unit (ALU), datapaths and      286 292 294 296
Arithmetic logic unit (ALU), MIPS      B32Ч38
Arithmetic logic unit (ALU), multicycle implementation      318Ч340
Arithmetic logic unit (ALU), single-cycle implementation      300Ч318
Arithmetic, Addition      170Ч176
Arithmetic, division      183Ч189
Arithmetic, fallacies and pitfalls      220Ч224
Arithmetic, floating point      189 191Ч220
Arithmetic, mean      257Ч258
Arithmetic, Multiplication      176Ч182
Arithmetic, signed and unsigned numbers      160Ч170
Arithmetic, subtraction      170Ч176
Arithmetic-logical instructions      292Ч293 298
Arithmetic-logical instructions, multiple-cycle implementation      327 329
Arithmetic-logical instructions, single-cycle implementation      300Ч318
ARM      D36Ч38
ARPANET      CD8.3:5 CD8.11:7
Arrays of logic elements      B18Ч19
Arrays, versus pointers      130Ч134
Art, restoration of      562Ч563
ASCII (American Standard Code for Information Interchange)      90Ч91
ASCII (American Standard Code for Information Interchange) versus binary numbers      162
Assembler directives      A5
assemblers      13 107Ч108 A4 10Ч17
Assembly language      13 107 A3Ч10 see
Assembly language, disadvantages of      A9Ч10
Assembly language, when to use      A7Ч9
Assert signal      290
Asserted signal      290 B4
Associativity, in caches      499Ч502
Asynchronous bus      582Ч583
Asynchronous inputs      ¬75Ч77
AT&T Bell Labs      CD7.9:8Ч9
Atanasoff, John      CD 1.7:3
Atomic swap operation      CD9.3:18
AUocate-on-miss      484
automatic storage class      85
Availability      573
Average Memory Access Time (AMAT)      IMD7:1
Bachman, Charles      CD8.11:4 5
Backpatching      A13
backplane      582
Backus, John      CD2.19:6 7
Barrier synchronization      CD9.3:15
Base 2 to represent numbers      160Ч161
Base address      55 100
Base register      55
base stations      CD8.3:9
Basic block      75
Basket, Forrest      CD7.9:9
Behavioral specification      B21
Bell Labs      CD7.9:8Ч9
Benchmarks      254Ч255
Benchmarks, EEMBC, 255      IMD4:17Ч18
Benchmarks, kernel      CD4.7:2 IMD4:7Ч8
Benchmarks, SPEC CPU      254Ч255 259Ч266 CD4.7:2Ч3 IMD4:7Ч8
Benchmarks, SPECweb      99 262Ч266
Benchmarks, synthetic      CD4.7:lЧ2 IMD4:11Ч12
Berkeley Computer Corp. (BCC)      CD7.9:8 9
Berkeley Software Distribution (BSD)      CD7.9:9
BernersЧLee, Tim      CD8.11:7
Biased notation      170 194
Big Endian      56 A43
Big-interleaved parity (RAID 3)      576Ч577
Bigelow, Julian      CD1.7:3
Binary digits (numbers)      12 60
Binary digits (numbers), adding and subtracting      170Ч176
Binary digits (numbers), ASCII versus      162
Binary digits (numbers), converting to decimal floating point      196
Binary digits (numbers), converting to decimals      164
Binary digits (numbers), hexadecimal-binary conversion table      62
Binary digits (numbers), scientific notation      191
Binary digits (numbers), use of      160Ч161
Binary point      191
bit error rate (BER)      CD8.3:9
Bit(s)      12 60
Bit(s) in a cache      479
Bit(s), dirty      521
Bit(s), fields      IMD2:13Ч14
Bit(s), least significant      161
Bit(s), map      18
Bit(s), most significant      161
Bit(s), reference/use      519
Bit(s), sign      163
Bit(s), sticky      215
Blaauw, Gerrit      CD6.13:2
BLNAC      CD1.7:4
Block, Barbara      156Ч157
Block-interleaved parity (RAID 4)      577Ч578
Blocking assignment      B24
Blocks, denned      470
Blocks, finding      540Ч541
Blocks, locating in caches      502Ч504
Blocks, placement of      538Ч540
Blocks, reducing cache misses with      496Ч502
Blocks, replacing      504 541Ч542
Bonding      30
Boolean algebra      B6
BoothТs algorithm      IMD3:5Ч9
Bounds check shortcut      168
Branch (es), addressing in      97Ч99 294Ч295
Branch (es), delay slot      423
Branch (es), delayed      297 382 418Ч419 A41
Branch (es), history table      421
Branch (es), loop      421Ч422
Branch (es), multiple-cycle implementation      327Ч328 336
Branch (es), not taken      295 418
Branch (es), prediction      382 421Ч423
Branch (es), prediction buffer      421
Branch (es), taken      295
Branch (es), target address      294Ч296
Branch (es), target buffer      423
Branch equal (beq)      294 297 300Ч318
Branch/control hazards      379Ч382 416Ч424
Branch/control hazards, delayed      297 382 418Ч419
Branch/control hazards, dynamic branch prediction      421Ч423
Branch/control hazards, not taken      295 418
Branch/control hazards, untaken      381
Branch/control hazards, Verilog and      CD6.7:8Ч9
Brooks, Fred, Jr.      CD6.13:2
Bubble sort      129
Burks, Arthur W., 48      CD1.7:3 CD3.10:1
buses      291Ч292
Buses, advantages/disadvantages of      581
buses, asynchronous      582Ч583
Buses, backplane      582
Buses, basics of      581Ч585
Buses, defined      581 B18Ч19
Buses, master      594
Buses, Pentium 4      585Ч587
Buses, processor-memory or I/O      582
Buses, shared      322Ч324
buses, synchronous      582Ч583
Buses, transaction      582
bypassing      376Ч377
Byte addressing      56
byte order      A43
C++      CD2.19:7
C, bit fields      IMD2:13Ч14
C, converting floating points to MIPS assembly code      209Ч213
C, development of      CD2.19:7
C, logical operations      68Ч71
C, overflows      172
C, procedures      81Ч88
C, sort example      121Ч129
C, strings      92Ч93
C, translating hierarchy      106Ч111
C, while loop in      74Ч75
Cache coherency, multiprocessor      CD9.3:12Ч20
Cache coherency, protocols      CD9.3:13 16Ч18
Cache coherency, snooping      CD9.3:13
Cache coherency, synchronization using      CD9.3:18Ч20
Cache-coherent nonuniform memory access (CC-NUMA)      CD9.4:22
Caches, accessing      476Ч482
Caches, associativity      499Ч502
Caches, basics of      473Ч491
Caches, bits in      479
Caches, blocks used to reduce misses      496Ч502
Caches, blocks, locating in      502Ч504
Caches, denned      473
Caches, direct-mapped      474Ч475 497
Caches, example of simple      474Ч476
Caches, fully associative      497
Caches, Intrinsity FastMATH processor example      485Ч487
Caches, mapping address to multiword block      480
Caches, memory      20
Caches, memory system design to support      487Ч491
Caches, misses, handling      482Ч483 496Ч502
Caches, multilevel      492 505Ч510
Caches, nonblocking      445 548
Caches, performance with increased clock rate      495Ч496
Caches, performance, measuring and improving      492Ч511
Caches, reducing miss penalty using multilevel      505Ч509
Caches, set associative      497 504
Caches, split      487
Caches, tags      475 504
Caches, three Cs model      543Ч545
Caches, valid bit      476
Caches, writes, handling      483Ч485
Cal TSS      CD7.9:8
callee      80 A23
caller      80 A23
Capacity misses      543
Carnegie Mellon University      CD6.13:5
Carrier signal      CD8.3:8
Carry lookahead      B38Ч47
Carry save adders      181 IMD3:17Ч18
Case statement      76
cathode ray tubes (CRTs)      18
Cause register      342
Cause Write      342
Central processor unit (CPU)      20
Central processor unit (CPU), execution time      244Ч245
Central processor unit (CPU), performance      245 246Ч253
Central processor unit (CPU), time      244Ч245
Cerf, Vint      CD8.11:7
Chamberlin, Donald      CD8.11:5
characters, Java      93Ч95
Chavin de Huantar      236Ч237
Chips      20 30
Clearing words in memory arrays and      130Ч132
Clearing words in memory arrays and, comparing both methods      133Ч134
Clearing words in memory arrays and, pointers and      132Ч133
Clock cycles      245 B47
Clock cycles per instruction (CPI)      248Ч251
Clock cycles per instruction (CPI) in multicycle CPU      330Ч331
Clock cycles, breaking execution into arithmetic-logical instruction      327 329
Clock cycles, breaking execution into branches      327Ч328
Clock cycles, breaking execution into decode instruction and register fetch      326Ч327
Clock cycles, breaking execution into fetch instruction      325Ч326
Clock cycles, breaking execution into jump      328
Clock cycles, breaking execution into memory read      329
Clock cycles, breaking execution into memory reference      327 328
Clock cycles, finite state machines      332
Clock cycles, multicycle implementation      318Ч340
Clock cycles, single-cycle implementation      300Ч318
Clock period      245 B47
Clock rate      245
Clock skew      B73Ч74
Clocking methodology      290Ч292 B47
Clocking methodology, edge-triggered      290Ч291 B47
Clocking methodology, level-sensitive      B74Ч75
Clocking methodology, tuning methodologies      B72Ч77
clocks      B47Ч49
CLU      CD2.19:7
1 2 3 4 5 6
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