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Название: Formal Verification: For Digital Circuit Design
Авторы: Perry D.L., Foster H.
Intended for hardware design engineers, this book introduces general verification techniques, compares them with formal verification techniques, and provides instructions for creating formal high level requirement. The authors discuss formal verification concepts for both applied Boolean and sequential verification, formal property checking, the process of creating a formal test plan, and state reduction techniques. The appendices list commonly used PSL statements for high level requirements and similar requirements specified in System Verilog syntax.