A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). Our study indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be replaced by a fully depleted technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved. A strong motivator for using the SOI CMOS technology instead of bulk CMOS seems to be the smaller gate leakage power consumption.