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Название: Switch-Level Timing Simulation of MOS VLSI Circuits
Авторы: Rao V., Overhauser D., Trick T.
This monograph reports our recent work on simulation-based methods for test generation. We have written it for CAD engineers, VLSI designers, test
engineers, and researchers.
Most people who deal with digital circuits, realize that test generation for
sequential circuits is a very difficult problem. The known algorithms, when
programmed, have proved to be rather inefficient and computationally expensive. In
the winter of 1986, we set out to look for a new solution. We noticed that
simulators and test generators manipulate the same circuit description but use distinctly
different algorithms. Simulators analyze logical behavior and delays of circuit
elements while test generators only analyze the logical behavior. However, the high
complexity of test generators makes it impractical to add any timing considerations