For almost a decade, the makers of DRAM ignored the growing problems of accessing data at rates matching the exponentially growing demands of new microprocessors. The increase in memory densities meant that the traditional
form of DRAM, with features and performance unchanged since the mid-70' s, actually worsened with each
generation from a systems perspective. A present-day DRAM offers an eighth or less of its capacity as an active
memory: the remainder of the chip is dead capacitance even in an active cycle. In addition, the data is not in a useful
format and the analog mess of timing parameters is a system designer's nightmare. Patches designed to increase raw
bandwidth helped only marginally at the cost of making the timing specifications almost unworkable.