The technological development is enabling production of increasingly complex electronic
systems. All those systems must be verified and tested to guarantee correct behavior. As the
complexity grows, testing is becoming one of the most significant factors that contribute to
the final product cost. The established low-level methods for hardware testing are not any
more sufficient and more work has to be done at abstraction levels higher than the classical
gate and register-transfer levels. This thesis reports on one such work that deals in particular
with high-level test generation and design for testability techniques.
The contribution of this thesis is twofold. First, we investigate the possibilities of generating
test vectors at the early stages of the design cycle, starting directly from the behavioral
description and with limited knowledge about the final implementation architecture. We have
developed for this purpose a novel hierarchical test generation algorithm and demonstrated
the usefulness of the generated tests not only for manufacturing test but also for testability
analysis.