Interconnect model reduction has emerged as one crucial operation for circuit analysis
in the last decade as a result of the phenomenon of interconnect dominance
of advanced VLSI technologies. Because interconnect contributes to a significant
portion of the system performance, we have to take into account the coupling effects
between subcircuit modules. However, the extraction of the coupling renders
many small fragments of parasitics. While the values of the parasitics are small, the
number of fragments is huge and this makes the accumulated effect non-negligible.
If left untreated, the amount of parasitics can gobble up the memory capacity and
consume long CPU time during circuit analysis