I have a VHDL background and this book was recommended to me. It made a smoooth transition into verilog. I read the book globally and then kept the book as a reference on my desk. If I needed something specific like file I/O and generating vectors, I used the example as a template to complete my verification. Also it helped to organize my files, like having one verification environment and easily plugging in tests by use of common tasks. Currently I am using Verilog and System Verilog, this book is still used regularly.