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| Ïîèñê ïî óêàçàòåëÿì |
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| Milutinovic V. — Computer Architecture: Concepts and Systems |
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| Ïðåäìåòíûé óêàçàòåëü |
Access stencil, definition 209
Actus, machine-independent language for SIMD machine 189
Adder design, gallium arsenide 103—104
Aerodynamic simulation, dataflow computation for 381—385
AeroSim 385—393
AeroSim, program analysis of 390t
Algol, for parallel processing 185
ALICE multiprocessor, two-level heirarchical system 418—419
ALICE system, determining parallelism in 431
ALICE, architecture, applications 331t
Alpha 345
ALU 77
AMPS, architecture, applications 331t
AMPS, determining parallelism in 431
APL Machine see "IBM APL Machine"
Applicative language 405
Applicative model of computation 138
Approximate greedy window control 293—294
AR-PANET, resource scheduling in 275
Architecture, computer, goals of 49—52
Architecture, computer, hardware requirements 51
Architecture, computer, language features 50—51
Architecture, computer, trends 52—56
Architectures, advanced microprocessors 3—47
Architectures, ALICE 331t
Architectures, AMPS 331t
Architectures, combinator-reduction 435
Architectures, Connection Machine 331t 336f
Architectures, Cray 2 320f
Architectures, DADO 331t 338f
Architectures, dataflow (Dennis) 440f
Architectures, DEL model for execution 41f
Architectures, direct execution 5 42—45
Architectures, FAIM-1 331t
Architectures, fault-tolerant computers 495—552
Architectures, functional programming 434—444
Architectures, functional programming supported by 415—453
Architectures, G-machine 434—437
Architectures, Guzman Machine 331t
Architectures, HEP-1 322f
Architectures, high-level language processors 3—47
Architectures, HLL computers, classification of 4—6
Architectures, IBM/RP3 321—323
Architectures, implementation issues 74—80 see
Architectures, indirect execution 5
Architectures, lambda-reduction 435
Architectures, language-corresponding 6 34—42
Architectures, language-directed 6 24—34
Architectures, Mago's tree machine 437—440
Architectures, Mago's tree machine, Manchester dataflow machine 440—442 443f
Architectures, MIMD machine 182
Architectures, MISD machine 182
Architectures, MIT Scheme-79/81 36f
Architectures, multiple-SIMID machine 183
Architectures, multiprocessor 135—177
Architectures, NON-VON supercomputer 331t 339f
Architectures, packaging constraints on 79—80
Architectures, parallel interference machine 343f
Architectures, partitionable-SIMD/MIMD machine 184
Architectures, PIM-D, ICOT 331t
Architectures, Pluribus 540f
Architectures, reduced instruction set computer (RISC) 48—83
Architectures, Remps 328f
Architectures, Sequoia 541f
Architectures, SIMD machine 180—182
Architectures, SISD machine 180
Architectures, SNAP 331t
Architectures, stack 25
Architectures, STAR 531f
Architectures, static dataflow 360—366
Architectures, Stratus FT 200 536—537
Architectures, supercomputers 309
Architectures, tagged token 360—361
Architectures, tagged-token data flow 143—144
Architectures, Tandem 533f
Architectures, Tandem Systems 534f
Architectures, THRISTLE, CMU 332t
Architectures, ZAPP 443—444
Architectures, ZMOB 332t
Array processors, definition 309
Array, definitions 367
Arrays, computation with 367—374
Arrays, smooth module example 367—371
Artificial intelligence machines 307—353
Artificial intelligence machines, applications 313—315
Artificial intelligence machines, associative memory in 312
Artificial intelligence machines, dynamic allocation in 312
Artificial intelligence machines, examples 330—344 331t
Artificial intelligence machines, expert systems 332
Artificial intelligence machines, future perspectives 344—347
Artificial intelligence machines, load-balancing in 312
Artificial intelligence machines, logical set operations required 312
Arvind's data flow machine vs. HEP 173
Arvind's data flow machine, organization 144f
Assembly language, role of, in computer architecture 52
Associative memory structures, bit-parallel CAM 195—196
Associative processing 193—196
Auto-regressive-moving-average, time series analysis 295
Availability, evaluation of fault-tolerant systems 508
Availability, system 503—504
Backup sparing 518—519
Banyan interconnection network, diagram 212f
Banyan interconnection network, SIMD machine 212f
BFL 87
BFL logic circuits, D-MESFETs in 87
Binary decision tree, dynamic-programming window control 297f 298
Binary N-cube configuration, ZAPP 443
Binary-divide window control 285—288
Bit-map synchronization 164—165
Bit-parallel CAM 195—196
Bit-serial CAM 196
Branch likely bit in Ridge 32 19—20
Branch likely bit, definition 19—20
Bridging, definition 509
Bulldog compiler, detection of parallelism 152 153—154
C.mmp, synchronization in 161
CAB see "Compare and branch instruction"
Cache memory 167—169
Cache memory, definition 167
Cache miss, definition 167
Cache/main memory compiler optimizations 123—124
Capability checking, fault/error detection 514
Cappello and Stieglitz transformation method 470—472
Carrier-sense multiaccess networks 276—277 278—279 see
CDC Cyber 205, speed performance of 310t
Cedar, cache coherence 168—169
Cedar, clustering tasks in 155
Cedar, comparison of, with other multiprocessors 172t
Cedar, control mechanisms in 171 173
Cedar, organization 147f
Cedar, parallel-parallel-serial control 147—148
Cedar, synchronization in 162—164
Central scheduler, definition 275
Centralized state-dependent scheduling 275
Chaining 161
Checkpointing, error recovery 520
Checkpointing, Synapse N + 1 537—538
Checksums, fault/error detection 513
Chen and Mead transformation method 484
Cheng and Fu transformation method 476—478
Circuit-switched network vs. message-switched network 203
CISC see "Complex instruction set computer"
Clustering, parallelism detection 154—155
Cm* multiprocessor 198—210
Cm* multiprocessor, memory references 199—200
Cm* multiprocessor, structure 198
Cohen, Johnsson, Weiser, Davis transformation method 461—463
Combinator-reduction architecture 435—436
Compact instruction formats see "Instruction formats compact"
Compare and branch (CAB) instruction 18
| Compiler design, CISC processors 115—116
Compiler design, gallium arsenide systems 115—125
Compiler design, RISC processors 115
Compiler design, silicon vs. GaAs systems 115—116
Compiler, implementation of memory hierarchy information control 113
Compiler, memory support 120—125
Compilers, detection of parallelism 152—153
Complex Instruction Set Computer (CISC) 4
Complex instruction set computer (CISC), timing hazard interlocks in 119
Computation, data-driven evaluation 422
Computation, demand-driven evaluation 422
Computation, large-scale, arrays 367—374
Computation, models of 138—139
Computation, sequential evaluation 422
Computational speed, increased by parallel processing 179
Computer architecture, goals of 49—52 see
Computer structures, taxonomy 525f
Computer systems, dependability 497—499
Computer systems, errors in 499—500
Computer systems, failures in 499—500
Computer systems, faults in 499—500
Computing, imperative model 406—407
Concurrent-Lisp processor, shared bus interconnection in 417
Conditional coding 108
Connection Machine, architecture, applications 331t
Connection Machine, components 335
Connection Machine, configuration 333 335
Connection Machine, message transfer in 335—336
Connection Machine, processor cell design 335 336f
Consistency checking, fault/error detection 514
content addressable memory (CAM) 193—196
Content addressable memory (CAM), hardware organization of 195f
Content addressable memory (CAM), operation of 194f
Contention parameters, definition 281
Contention parameters, estimating distribution functions of 295—296
Contention slot, definition 277
Context-based instructions 108—109
Contour extraction 196
Contour tracing 197
Control model, classification 141—149
Control unit design 76—77
Control unit design, function of 76
Control unit design, problems 76—77
Control, parallel-parallel, two-level 143—144
Control, parallel-serial 142
Control, serial, single-level 142
Control, serial-parallel 143
Copy-back method 112
Copying structures, FP machines 427
Cosmic Cube, architecture and nodes connection 145f
Cosmic Cube, comparison of, with other multiprocessors 172t
Cosmic Cube, control mechanisms in 171
Cosmic Cube, message passing 170
Cosmic Cube, parallel-serial control 145
Cosmic Cube, synchronization in 165
Coverage 505
Cray 1, gallium arsenide implementation 95
Cray 1, key parameters 317t
Cray 1, serial-parallel control 143
Cray 1, speed performance of 310t
Cray 2, architecture 320f
Cray 2, configuration 319—320
Cray 2, cycle time 319
Cray 2, key parameters 317
Cray 2, speed performance of 310t
Cray 2, technological innovations 320
Cray 2, UNIX operating system 320
Cray 3, GaAs circuits 320
Cray 3, key parameters 317t
Cray 3, performance 320
Cray 3, speed performance of 310t
Cray operating system 317
Cray S-MP, speed performance of 310t
Cray supercomputers 317—320
Cray supercomputers, key parameters 317t
Cray X-MP, clustering tasks in 155
Cray X-MP, comparison with other multiprocessors 172t
Cray X-MP, compiler 319
Cray X-MP, configuration 317—319
Cray X-MP, control mechanisms in 171
Cray X-MP, CPUs 317—318
Cray X-MP, cycle time 317
Cray X-MP, key parameters 317t
Cray X-MP, SSD 318—319
Cray X-MP, synchronization in 161
Cray X-MP, time multiplexing 169
Cray X-MP-2, serial-parallel-parallel control 143
Cray X-MP-2, synchronization in 165
Cray X-MP-2, system organization 143f
Crossbar switch 166 227—228
Cube network 229—232
Cube network, definition 229
Cube network, MIMD environment 231
Cube network, partitioned 231—232
Cube network, partitioning 232f
Cube network, SIMD environment 230—231
D-MESFETs 86
D-MESFETs in BFL, SDFL logic circuits 87
DADO multiprocessor 337—339
DADO multiprocessor, architecture, applications 331t
DADO multiprocessor, binary tree structure 337 338f
DADO multiprocessor, PEs in 337
Data manipulator networks 252—258
Data manipulator networks, broadcast routing tags in 256
Data manipulator networks, definition 252
Data manipulator networks, full routing tags in 254—256
Data manipulator networks, network control 254—257
Data manipulator networks, network structure 252—254
Data manipulator networks, partitioning 257—259
Data manipulator networks, tasks performed by 253
Data path design 77—79
Data path, components of 77
Data path, MIPS 77 78f
Data representation 426—427
Data representation, FP machines 426—427
Data reusability, in RISCs 8—9
Data trees, definition 213
Data-driven execution, model of parallel sequencing 140—141
Dataflow computation 354—404
Dataflow computation, aerodynamic simulation 381—385
Dataflow computation, AeroSim 385—393
Dataflow computation, analysis of program structure 377—381
Dataflow computation, application block tridiagonal systems 393—398
Dataflow computation, application of 399
Dataflow computation, determinancy 358
Dataflow computation, examples of computing problems for 398—399
Dataflow computation, history 354—355
Dataflow computation, language choice 355
Dataflow computation, model 355
Dataflow computation, models for 357—360
Dataflow computation, pipelining in 359—360
Dataflow computation, static architecture 360—366
Dataflow computation, Val compiler for 374—377
Dataflow instructions, elements of 363f
Dataflow instructions, pipelined execution 363f
Dataflow instructions, quadratic function code 364 365f
Dataflow language 405
Dataflow machines, processing elements in 362—364
Dataflow machines, prototypes 361
Dataflow machines, requirements for 361—364
Dataflow program graphs 355
Dataflow supercomputers, resource sharing systems 270 270f
DCFL 87
DCFL logic circuits in MODFET devices 89
DCFL logic circuits, E-MESFETs and D-MESFETs in 88—89
Deadlock avoidance, FP machines 431 — 432
DEC VLSI VAX 33—34
DEC VLSI VAX, configuration 33
DEC VLSI VAX, cycle time 34
DEC VLSI VAX, memory management 33
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