Our workshop is being held in the midst of a watershed era of growth and innovation in the EDA industry, most notably within the "back-end" domains of physical design and physical verification. Timing-, signal integrity- and power-consciousness have rapidly become mainstream design requirements, with reliability and yield just around the corner. Many classic techniques have broken down, from the design of cell libraries to place-and-route to physical verification. That this sea change is partly due to the continued scaling of process technology (weaker drivers driving more resistive interconnects, lower supply voltages reducing noise margins, slew rates affecting signal integrity and timing, neighboring interconnects coupling more noticeably, ...) is well recognized. But the changing nature of the semiconductor business itself - the changing nature of design teams and design projects (more design starts, shorter (synthesis-driven) design cycles, ... ) has had an equally profound impact on our context.