Нашли опечатку? Выделите ее мышкой и нажмите Ctrl+Enter
Название: Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
Авторы: Radecka R., Zilic Z.
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.