Katarzyna Radecka, Zeljko Zilic — Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
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Название: Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Frontiers in Electronic Testing)
Авторы: Katarzyna Radecka, Zeljko Zilic
Аннотация:
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
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