This book constitutes the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007, held in Gothenburg, Sweden, in September 2007.

The 36 revised full papers and 19 revised poster papers presented together with the abstracts of 3 key notes and 2 industrial papers were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on high-level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, low power techniques and applications, as well as design challenges in real-life projects.